Cryptosystem designers frequently assume that secrets will be manipulated in closed, reliable computing environments. Unfortunately, actual computers and microchips leak information about the operations they process. This paper examines specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. We also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.

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Differential Power Analysis

A disclosed player tracking unit provides a display and a player tracking controller designed or configured to provide a web-browser on the display. The player tracking unit may include one or more input devices that can receive selections associated with the web-browser. Furthermore, the player tracking unit can include a multimedia board for processing digitally formatted program files for output on the display.

Player tracking communication mechanisms in a gaming machine

A data collection device comprising: a data collection subsystem; a wireless communication device; a dedicated panic button; and a processor that, responsive to a user activating the dedicated panic button, uses the wireless communication device to cause a message to be sent to a designated emergency contact.

Panic button for data collection device

Protected memory locations or contents are associated with respective corresponding keys. Memory operations that alter the protected memory locations or contents are denied unless the corresponding keys are provided. In one implementation, the keys are stored in a key store on an electronic device and accessible only to a memory access manager that controls access to the protected memory and contents. In order to alter a protected memory location or contents, an electronic device component must first obtain the required key or keys from another source, such as a source from which data to be written to a protected memory location is received, and then provide the or each key to the memory access manager. After a memory operation has been permitted or completed, any keys provided to the memory access manager by an electronic device component are rendered inaccessible, such as by deleting the keys from memory.

Memory protection systems and methods for writable memory

A novel FLASH-based EEPROM cell, decoder, and layout scheme are disclosed to eliminate the area-consuming divided triple-well in cell array and allows byte-erase and byte-program for high P/E cycles Furthermore, the process-compatible FLASH cell for EEPROM part can be integrated with FLASH and ROM parts so that a superior combo, monolithic, nonvolatile memory is achieved Unlike all previous arts, the novel combo nonvolatile memory of the present invention of ROM, EEPROM and FLASH or combination of any two is made of one unified, fully compatible, highly-scalable BN+ cell and unified process In addition, its cell operation schemes have zero array overhead and zero disturbance during P/E operations The novel combo nonvolatile memory is designed to meet the need in those markets requiring flexible write size in units of bytes, pages and blocks at a lower cost

Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

A microcontroller for security applications includes an encryption unit between a bus and a functional unit. The encryption unit includes a gate and a key register. A memory is provided with a further encryption unit whose gate is connected between the register and the gate of the first encryption unit. As a result, the transferred information item is available in encrypted form at any point on the bus.

Microprocessor configuration with encryption

The invention relates to a method for determining a physical address from a virtual address, whereby a mapping rule is implemented between the virtual address and the physical address in the form of a hierarchical tree structure comprising compressed nodes. According to said method, a compression indicator contained in the mapping rule is first read (1300). Then, a section of the virtual address, which is assigned to the node level under consideration, is read (1310). An entry in the node list of the node currently under consideration is determined (1320) using the compression indicator and the virtual address section. The entry that has been determined is read (1330) and the physical address can then be directly determined, if the node level under consideration was the lowest node level in the hierarchy. If there are additional node levels to be processed, the previous steps are repeated for the determination (1340) of the physical address for compressed nodes of lower hierarchy levels, until the lowest node level in the hierarchy has been reached. For addressing schemes, in which the virtual address space is greater than the physical address space, storage space can be saved by the compression of the node lists, which in their uncompressed form contain a number of zero entries, thus providing space for other data.

Device and method for determining a physical address from a virtual address, using a hierarchical mapping rule comprising compressed nodes

Device for generating random numbers having a pseudo random number generator, a memory and a sequential controller. The pseudo random number generator generates a deterministic random number sequence after an initialization using an initialization value. The memory stores initialization information, wherein the initialization information is derived from a true random number or corresponds to the true random number. The sequential controller initializes the pseudo random number generator at start-up using the initialization information or the information derived from the initialization information, stores an intermediate state of the pseudo random number generator or information derived from the intermediate state in the memory at a turn-off of the pseudo random number generator, and uses the intermediate state or the information derived from the intermediate state for an initialization of the pseudo random number generator at a renewed start-up.

Device and method for generating random numbers using a pseudo random number generator

A condenser includes a condensation zone for condensing vapor to be condensed in an operating liquid, the condensation zone being formed as a volume zone including a top end, a bottom end and a lateral boundary between the top end and the bottom end, and a vapor introduction zone extending along the lateral end of the condensation zone and being configured to feed vapor to be condensed into the condensation zone laterally via the lateral boundary.

Condenser, method for condensing and heat pump

The invention relates to an electronic data processing device comprising a processing unit (CPU) which is connected to at least one memory (ROM, EEPROM) via a bus. An encoding unit (VE) is assigned to the processing unit (CPU). At least one secret key (Key1, Key2) is stored in the memory or in one of the memories (ROM, EEPROM) and at least all security-relevant data is stored in the memory or memories (ROM, EEPROM) in encoded form. A comparator (V) for comparing the stored secret key (Key1, Key2) with a keyword (SW) to be entered by a user controls a switching unit (SE; MUX) controlling the encoding unit (VE), so that stored data can be decoded only if the comparison is positive.

Holger Sedlak

Papers

Microprocessor configuration with encryption

Device and method for determining a physical address from a virtual address, using a hierarchical mapping rule comprising compressed nodes

Device and method for generating random numbers using a pseudo random number generator

Condenser, method for condensing and heat pump

Electronic data processing device and system