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Hong-Ji Lee

Bio: Hong-Ji Lee is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: Etching (microfabrication) & Wafer. The author has an hindex of 7, co-authored 34 publications receiving 1009 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2008
TL;DR: In this paper, a novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology, which uses a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, and excellent memory performances such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles) have been demonstrated in the memory device.
Abstract: A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

634 citations

Proceedings ArticleDOI
01 Dec 2010
TL;DR: In this article, a modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles, and the performance of the HfO X-based bipolar resistive memory was improved.
Abstract: The memory performances of the HfO X based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

256 citations

Proceedings ArticleDOI
01 Dec 2012
TL;DR: In this article, an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency is presented.
Abstract: We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

51 citations

Patent
24 May 2011
TL;DR: In this article, a method for providing electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device is described, where a portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level.
Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device Each contact level comprises conductive and insulation layers A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level A set of N masks is used to etch the contact openings up to and including 2N contact levels Each mask is used to etch effectively half of the contact openings When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels A dielectric layer may be formed on the sidewalls of the contact openings Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls

37 citations

Patent
24 May 2011
TL;DR: In this paper, a set of N masks are used to etch the contact openings up to and including 2 N contact levels, and when N is 3, a first mask etches one contact level, a second mask enforces two contact levels.
Abstract: A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2 N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

33 citations


Cited by
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Journal ArticleDOI
02 May 2012
TL;DR: The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide resistive switching random access memory (RRAM) are discussed, with a focus on the use of RRAM for nonvolatile memory application.
Abstract: In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

2,295 citations

Journal ArticleDOI
TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Abstract: Various new nonvolatile memory (NVM) technologies have emerged recently. Among all the investigated new NVM candidate technologies, spin-torque-transfer memory (STT-RAM, or MRAM), phase-change random-access memory (PCRAM), and resistive random-access memory (ReRAM) are regarded as the most promising candidates. As the ultimate goal of this NVM research is to deploy them into multiple levels in the memory hierarchy, it is necessary to explore the wide NVM design space and find the proper implementation at different memory hierarchy levels from highly latency-optimized caches to highly density- optimized secondary storage. While abundant tools are available as SRAM/DRAM design assistants, similar tools for NVM designs are currently missing. Thus, in this paper, we develop NVSim, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash. NVSim is successfully validated against industrial NVM prototypes, and it is expected to help boost architecture-level NVM-related studies.

1,100 citations

Journal ArticleDOI
21 Oct 2010
TL;DR: In this paper, the authors review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the non-volatile functionalities.
Abstract: In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device.

824 citations

Journal ArticleDOI
26 Aug 2011-ACS Nano
TL;DR: This study shows experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems and confirms that not only the shape or the total number of stimuli is influential, but also the time interval between stimulation pulses plays a crucial role in determining the effectiveness of the transition.
Abstract: “Memory” is an essential building block in learning and decision-making in biological systems. Unlike modern semiconductor memory devices, needless to say, human memory is by no means eternal. Yet, forgetfulness is not always a disadvantage since it releases memory storage for more important or more frequently accessed pieces of information and is thought to be necessary for individuals to adapt to new environments. Eventually, only memories that are of significance are transformed from short-term memory into long-term memory through repeated stimulation. In this study, we show experimentally that the retention loss in a nanoscale memristor device bears striking resemblance to memory loss in biological systems. By stimulating the memristor with repeated voltage pulses, we observe an effect analogous to memory transition in biological systems with much improved retention time accompanied by additional structural changes in the memristor. We verify that not only the shape or the total number of stimuli is i...

810 citations

01 Jan 2010
TL;DR: The challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device are summarized.
Abstract: In this paper, we review the recent progress in the resistive random access memory (ReRAM) technology, one of the most promising emerging nonvolatile memories, in which both electronic and electrochemical effects play important roles in the nonvolatile functionalities. First, we provide a brief historical overview of the research in this field. We also provide a technological overview and the epoch-making achievements, followed by an account of the current understanding of both bipolar and unipolar ReRAM operations. Finally, we summarize the challenges facing the ReRAM technology as it moves toward the beyond-2X-nm generation of nonvolatile memories and the so-called beyond complementary metal-oxide-semiconductor (CMOS) device.

766 citations