Horng-Yee Chou

Bio: Horng-Yee Chou is an academic researcher. The author has contributed to research in topics: Serial port & Controller (computing). The author has an hindex of 1, co-authored 1 publications receiving 106 citations.

Serial Interface to Flash-Memory Chip Using PCI-Express-Like Packets and Packed Data for Partial-Page Writes

Abstract: A serial flash-memory chip has a serial-bus interface to an external controller. A flash-memory block in the serial flash-memory chip can be read by the external controller sending a read-request packet over the serial bus to the serial flash-memory chip, which reads the flash memory and sends the data back in a data-payload field in a completion packet. Data in a write-request packet is written to the flash memory, and a message packet sent back over the serial bus. The serial bus can be a Peripheral Component Interconnect (PCI) Express bus with bi-directional pairs of differential lines. Packets have modified-PCI-Express headers that define the packet type and data-payload length. Vendor-defined packets can send flash commands such as reset, erase, or responses after operations such as program or erase. A serial engine and microcontroller or state machine are on the serial flash-memory chip.

Multiple independent serial link memory

Abstract: An apparatus, system, and method for controlling data transfer between a serial data link interface and memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple serial data links and multiple memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

PCI Express-Compatible Controller And Interface For Flash Memory

Abstract: A PCI Express-compatible flash device can include one or more flash memory modules, a controller, and an ExpressCard interface. The controller can advantageously provide PCI Express functionality as well as flash memory operations, e.g. writing, reading, or erasing, using the ExpressCard interface. A PIO interface includes sending first and second memory request packets to the flash device. The first memory request packet includes a command word setting that prepares the flash device for the desired operation. The second memory request packet triggers the operation and includes a data payload, if needed. A DMA interface includes sending the second memory request from the flash device to the host, thereby triggering the host to release the system bus for the DMA operation.

System and method of reading non-volatile computer memory

Abstract: The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a data sector of the non-volatile computer memory. The first portion of the redundant memory area includes data associated with the data sector. The first portion of the redundant memory area includes a cyclic redundancy check code.

Flash / phase-change memory in multi-ring topology using serial-link packet interface

Abstract: A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.

Scalable routing and addressing

Abstract: PCI Express transactions can be transmitted via a shared PCI Express infrastructure. At an infrastructure ingress point an additional header comprising at least a source identifier and a target identifier is generated for a transaction packet that comprises a header portion, a data portion and an end-to-end CRC portion. The transaction packet is then transmitted with the additional header from the ingress point to an egress point. At the egress point the additional header is removed. The additional header can further include a resource key. It can further include protection information such as a CRC.