https://iopscience.iop.org/article/10.35848/1882-0786/abc787/pdf

Defect engineering in SiC technology for high-voltage power devices

: The fabrication of a silicon carbide (SiC) junction field effect transistor (J-FET) was shown practicable. Several amplifier designs were breadboarded with silicon devices to study the required parameters. A simplified building block amplifier was constructed and tested. (Author)

High Temperature Electronics.

Silicon carbide (SiC) power transistors have started gaining significant importance in various application areas of power electronics. During the last decade, SiC power transistors were counted not only as a potential, but also more importantly as an alternative to silicon counterparts in applications where high efficiency, high switching frequencies, and operation at elevated temperatures are targeted. Various SiC device designs have been proposed and excessive investigations in terms of simulation and experimental studies have shown their advantageous performance compared to silicon technology. On a system-level, however, the design of gate and base drivers for SiC power transistors is very challenging. In particular, a sophisticated driver design is not only associated with properly switching the transistor and decreasing the switching power losses, but also it must incorporate protection features, as well as comply with the electromagnetic compatibility. This paper shows an overview of the gate and base drivers for SiC power transistors which have been proposed by several highly qualified scientists. In particular, the basic operating principle of each driver along with their applicability and drawbacks are presented. For this overview, the three most successful SiC power transistors are considered: junction-field-effect transistors, bipolar-junction transistors, and metal-oxide-semiconductor field-effect transistors. Last but not least, future challenges on gate and base drivers design are also presented.

Gate and Base Drivers for Silicon Carbide Power Transistors: An Overview

Focused ion beam technology and applications.

The significant advance of power electronics in today's market is calling for high-performance power conversion systems and MEMS devices that can operate reliably in harsh environments, such as high working temperature. Silicon-carbide (SiC) power electronic devices are featured by the high junction temperature, low power losses, and excellent thermal stability, and thus are attractive to converters and MEMS devices applied in a high-temperature environment. This paper conducts an overview of high-temperature power electronics, with a focus on high-temperature converters and MEMS devices. The critical components, namely SiC power devices and modules, gate drives, and passive components, are introduced and comparatively analyzed regarding composition material, physical structure, and packaging technology. Then, the research and development directions of SiC-based high-temperature converters in the fields of motor drives, rectifier units, DC-DC converters are discussed, as well as MEMS devices. Finally, the existing technical challenges facing high-temperature power electronics are identified, including gate drives, current measurement, parameters matching between each component, and packaging technology.

/pdf/silicon-carbide-converters-and-mems-devices-for-high-ec66fc2sm9.pdf

Silicon Carbide Converters and MEMS Devices for High-temperature Power Electronics: A Critical Review

Implantation-free mesa-etched ultra-high-voltage (0.08 mm2) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm2 is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain

By developing a two-dimensional (2D) full quantum simulation, the attributes of carbon nanotube field-effect transistors (CNTFETs) in different temperatures have been comprehensively investigated. Simulations have been performed by employing the self-consistent solution of 2D Poisson-Schrodinger equations within the nonequilibrium Green's function (NEGF) formalism. Principal characteristics of CNTFETs such as current capability, drain conductance, transconductance, and subthreshold swing (SS) have been investigated. Simulation results present that as temperature raises from 250 to 500 K, the drain conductance and on-current of the CNTFET improved; meanwhile the on-/off-current ratio deteriorated due to faster growth in off-current. Also the effects of temperature on short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and threshold voltage roll-off have been studied. Results show that the subthreshold swing and DIBL parameters are almost linearly correlated, so the degradation of these parameters has the same origin and can be perfectly influenced by the temperature.

/pdf/temperature-dependence-of-electrical-characteristics-of-4y8nv7ohke.pdf

Temperature dependence of electrical characteristics of carbon nanotube field-effect transistors: a quantum simulation study

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/ $\mathrm{cm}^{2}$ is obtained for the device with an active area of 0.065 $\mathrm{mm}^{2}$ . A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific on-resistance ( $R_{\mathrm{{\scriptstyle ON}}}$ ) of 28 m $\Omega \cdot {\rm cm^{2}}$ was obtained.

/pdf/5-8-kv-implantation-free-4h-sic-bjt-with-multiple-shallow-4j2025208l.pdf

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

In this paper, for the first time, a novel power partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor is proposed with dual p- and n- charge accumulation (CA) layers near the source and the drain (DCAL-PSOI). Two new high electric field peaks are introduced by the two p- and n- CA layers in the proposed structure. Hence, a more uniform electric field is obtained due to modulation of the electric field in the drift region by the charges located in the p- and n- CA layers and buried oxide surface. Therefore, the vertical breakdown voltage (BV) is significantly improved by reducing the high bulk electric field around the source and drain regions. The influences of the proposed structure parameters on device characteristics are analyzed. For the DCAL-PSOI LDMOS with a 120-μm drift region length, the maximum BV of 1317 V is obtained by the simulation, while at the same drift region length, the maximum BVs of the conventional PSOI (C-PSOI) and conventional silicon-on-insulator (C-SOI) devices are 628 and 330 V, respectively. Moreover, the device exhibits a superior specific on-resistance (Ron, sp) of 0.34 Ω·cm2, which shows that the on-resistance of the optimized DCAL-PSOI are decreased by 91%-95% in comparison to the C-PSOI. The superior BV and Ron, sp yield to a power figure of merit (BV2/Ron, sp) of 5.1 MW/cm2. Also, the Si window alleviates the self-heating effect, and the maximum temperature of the proposed structure reduces as compared with the C-PSOI and C-SOI devices.

Hossein Elahipanah

Papers

15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain

Temperature dependence of electrical characteristics of carbon nanotube field-effect transistors: a quantum simulation study

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

A 1300-V 0.34- $\Omega\cdot\hbox{cm}^{2}$ Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers

Simulation and optimization of high breakdown double-recessed 4H-SiC MESFET with metal plate termination technique