Hossein Fariborzi

Bio: Hossein Fariborzi is an academic researcher from King Abdullah University of Science and Technology. The author has contributed to research in topics: CMOS & Logic gate. The author has an hindex of 13, co-authored 59 publications receiving 773 citations. Previous affiliations of Hossein Fariborzi include University of Malaya & Massachusetts Institute of Technology.

Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications

Abstract: This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications

Abstract: Due to transistor leakage, CMOS circuits have a well-defined lower limit on their achievable energy efficiency [1]. Once this limit is reached, power-constrained applications will face a cap on their maximum throughput independent of their level of parallelism. Avoiding this roadblock requires an alternate switching device with steeper sub-threshold slope—i.e., lower V DD /I on for the same I on /I off [2]. One promising class of such devices with nearly ideal I on /I off characteristics are electro-statically actuated micro-electro-mechanical (MEM) switches [6]. Although mechanical movement makes MEM circuit delay significantly larger than that of CMOS, we have recently shown that with optimized circuit topologies MEM switches may potentially enable ∼10x lower energy over CMOS at up to ∼100MHz frequencies [3].

EAMTR: Energy aware multi-tree routing for wireless sensor networks

Abstract: IEEE 802.15.4 is the prevailing standard for low-rate wireless personal area networks. It specifies the physical layer and medium access control sub-layer. Some emerging standards such as ZigBee define the network layer on top of these lower levels to support routing and multi-hop communication. Tree routing is a favourable basis for ZigBee routing because of its simplicity and limited use of resources. However, in data collection systems that are based on spanning trees rooted at a sink node, non-optimal route selection, congestion and uneven distribution of traffic in tree routing can adversely contribute to network performance and lifetime. The imbalance in workload can result in hotspot problems and early energy depletion of specific nodes that are normally the crucial routers of the network. The authors propose a novel light-weight routing protocol, energy aware multi-tree routing (EAMTR) protocol, to balance the workload of data gathering and alleviate the hotspot and single points of failure problems for high-density sink-type networks. In this scheme, multiple trees are formed in the initialisation phase and according to network traffic, each node selects the least congested route to the root node. The results of simulation and performance evaluation of EAMTR show significant improvement in network lifetime and traffic distribution.

Analysis and demonstration of MEM-relay power gating

Abstract: This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with today's relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

Cascaded Logic Gates in Nanophotonic Plasmon Networks

Abstract: Modern electronics based on semiconductors is meeting the fundamental speed limit caused by the interconnect delay and large heat generation when the sizes of components reach nanometer scale. Photons as a carrier of the information are superior to electrons in bandwidth, density, speed, and dissipation. More over, photons could carry intensity, polarization, phase, and frequency information which could break through the limitation of binary system as in electronic devices. But due to the diffraction limitation, the photonic components and devices can not be fabricated small enough to be integrated densely. Surface plasmon polariton is quanta of collective oscillations of free electrons excited by photons in metal nanostrucrures, which offers a promising way to manipulate light at the nanoscale and to realize the miniaturization of photonic devices. Hence, plasmonic circuits and devices have been proposed for some time as a potential strategy for advancing semiconductor-based computing beyond the fundamental performance limitations of electronic devices, as epitomized by Moore's law. A variety of individual plasmonic nanodevices have been intensively studied recently, but the crucial and necessary step to enable nanophotonic circuits for future information technology, namely cascade logics integrated on-chip, has not been achieved. Here we demonstrate that a nanophotonic binary logic NOR gate can be realized by cascading plasmonic OR and NOT gates in four-terminal nanowire networks. We explain the operating principle for the device based on quantum dot luminescence imaging, which reveal the interferences for different logic functions between propagating plasmon wave packets in the nanowire network in great detail. Since the NOR gate is logic complete, i.e. any Boolean logic gate can be constructed from it, our results could have a key role in defining a viable path for the development of novel subwavelength optical processor architectures.

Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse

Abstract: Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip's transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches — the four horsemen — that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.