Hsien-Ku Chen

Bio: Hsien-Ku Chen is an academic researcher from National Taiwan University. The author has contributed to research in topics: CMOS & Wideband. The author has an hindex of 9, co-authored 23 publications receiving 356 citations.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $ -Match Input Network

Abstract: This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

Abstract: A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW-1 /mm2 ) which is the best results among all previous reported CMOS-based wideband LNA.

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

Abstract: This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

A mm-wave CMOS multimode frequency divider

Abstract: The availability of unlicensed mm-wave bands has fueled the research and development of mm-wave wireless systems. If different frequency bands can be operated from one signal source, it will reduce the circuit size and power consumption, leading to compact systems. For example, the frequencies 38, 57, 76GHz in 38, 60 and 77GHz bands can be generated by using only one PLL, as illustrated in Fig. 16.4.1. To address this requirement, in this paper, a multiband multimode injection-locked frequency divider (M-ILFD) is presented that meets the requirements for 38 and 57GHz applications.

A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13 $\mu$ m CMOS

Abstract: An intrinsic-tuned, 68 GHz voltage controlled oscillator (VCO) without an extra on-chip accumulation-mode metal oxide semiconductor (MOS)-varactor is demonstrated in a standard, 0.13 mum CMOS technology. This VCO exhibits phase noises of -98.4 dBc/Hz and -115.2 dBc/Hz at 1 and 10 MHz offset, respectively, along with a tuning range of 4.5 % even under a small power consumption of 4.32 mW. Besides, the highest figure-of-merit (taking frequency tuning range into account) of -182 dBc/Hz under the 1 MHz offset condition is achieved among all previously reported >60 GHz CMOS-based VCOs, which is attributed to the proposed intrinsic tuning mechanism.

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

Abstract: This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

Abstract: Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

A Single-Chip Dual-Band 22–29-GHz/77–81-GHz BiCMOS Transceiver

Abstract: A clear trend in wireless applications during the last decade has been the push towards higher integration, and multi-mode and multi-band operation, in order to enable low-cost high-functionality consumer devices. As the deployment of silicon-based MMW technology becomes widespread, similar trends may be expected in the MMW space

Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique

Abstract: Two inductorless wideband low-noise amplifiers (LNAs) fabricated in a 65-nm CMOS process are presented. By using the gain-enhanced noise-canceling technique, the gain at noise-cancelling condition is increased, while the input matching is maintained. The first work is a common-source LNA with resistive shunt feedback. It achieves a maximum power gain of 10.5 dB, a bandwidth of 10 GHz, a noise figure (NF) of 2.7-3.3 dB, and an IIP3 of -3.5 dBm. The power consumption is 13.7 mW from a 1-V supply, and the area is 0.02 mm 2. The second work is a common-gate LNA. It achieves a maximum power gain of 10.7 dB, a bandwidth of 5.2 GHz, a NF of 2.9-5.4 dB, and an IIP3 of -6 dBm. The power consumption is 7 mW from a 1-V supply, and the area is 0.03 mm 2. Experimental results demonstrate that the first LNA shows the largest bandwidth, and the second LNA has the lowest power consumption among the inductorless wideband LNAs.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $ -Match Input Network

Abstract: This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.