Hua-Yu Liu

Bio: Hua-Yu Liu is an academic researcher from Hewlett-Packard. The author has contributed to research in topics: Photomask & Photolithography. The author has an hindex of 4, co-authored 4 publications receiving 163 citations.

Application of alternating phase-shifting masks to 140-nm gate patterning: II. Mask design and manufacturing tolerances

Abstract: In this paper we present the results of experimental patterning 140 nm poly gates withdouble-exposure alternating phase-shifting masks (PSM) using a Nikon EX- 1 (KrF,0.42NA) stepper. We show that: systematic intrafield line width variations can becontrolled within 10 nm (3), interfield variations across the wafer to within 6 nm (3),and total variation across the wafer held to within 15 nm (3), with a target k1 factor of k1=0.237 (140 nm target gate lengths). We also present the results of studies addressingseveral issues related to the production application of alternating PSM' s, including mask manufacturing tolerances and full chip PSM design capabilities. We show that, incomparison to conventional binary masks, alternating PSM's reduce the criticality of mask line width control and reduce the sensitivity to mask defects. Furthermore tolerance to PSM phase errors can be significantly improved by placing a chrome regulator between phase-shifters. Automatic, high-speed full chip design of alternating strong PSMis now possible.Keywords: Optical lithography, Phase-shifting masks, line width variations, CD control

Wafer printability simulation accuracy based on UV optical inspection images of reticle defects

Abstract: As semiconductor processes have moved towards lower k 1 and mask inspection equipment has moved into the UV range, more subtle reticle defects have been found to cause manufacturing problems. Lower k 1 and new lithography processes and reticle technologies, such as OPC and PSM, have made it difficult to determine the significant and these defects. This paper reports on the development of a simulation tool that will improve the yield and productivity of photomask manufacturers and wafer manufacturers by improving reticle defect assessment. This study demonstrates the accuracy of simulation software that predicts resist patterns based on sophisticated modeling software that uses optical images obtained from a state-of-the-art UV optical inspection system. A DUV 4X reduction stepper was used to print a reticle with programmed defects across an exposure/focus matrix, with the minimum feature size being 200 nm. Quantitative comparisons between predicted and measured wafer CDs were made. In summary, it was found that the simulation software based solely on aerial images predicted absolute CDs with limited accuracy, but differential CDs with limited accuracy, but differential CDs, obtained by utilizing both the reference and defect images, were predicted accurately. Comparison of simulations using both reticle SEM images and optical reticle inspection images showed good agreement, demonstrating the accuracy and high resolution of the optical reticle inspection images. Application of differential aerial images to a simple test case showed that it was possible to identify and therefore eliminate a significant number of defects that did not print, thereby improving defect assessment.

Application of alternating phase-shifting masks to 140-nm gate patterning: linewidth control improvements and design optimization

Abstract: In this paper we show that the problem of intrafield line width variations can be effectively solved through a novel application of alternating phase-shifting mask (PSM) technology. To illustrate its advantages, we applied this approach to produce 140 nm transistor gates using DUV (248 nm wavelength, KrF) lithography. We show that: systematic intrafield line width variations can be controlled to within 10 nm (3 (sigma) ), and variations across the wafer held to within 15 nm (3 (sigma) ), with a target k1 factor of K1 equals 0.237 (140 nm target gate lengths).

Lithography process calibration with applications in defect printability analysis

Abstract: Lithography process simulation has proven to be a useful and effective tool for process characterization, namely, properly characterize critical dimension (CD) variations from the design that are caused by proximity effects and distortions introduced by the patterning tool, reticle, resist processing and etching. Accurate lithography process simulator further enables process engineers to automate the tasks of advanced mask design, verification and inspection that are used in deep-sub-micron semiconductor manufacturing. However, to get the most benefit from process simulations, we should properly calibrate the simulation model according to the process to be characterized. That is, given a representative set of CD measurements obtained from the process, we fine-tune the process model parameters so that the simulated/predicted CDs well match the measured CDs. By doing so, we can ensure to some extent that process simulations give sensible results to be used in the design analysis, verification and inspection applications. In this paper, we would like to demonstrate the possibility of obtaining an accurate process model for lithography process simulations via model calibration. We will also demonstrate the accuracy of calibrated process simulations by applying the calibrated model in mask defect printability analysis. For simplicity, the process model and the algorithms used in model calibration will not be discussed in this article but in our future publications. In Section 2, we present the characterization and calibration of a 0.18 micrometer DUV lithography process using positive chemically amplified resist (APEX-E) as an example. We describe the test pattern selections, the calibration process, and the performance of the calibrated model in terms of predicting the CD measurements given test patterns. In Section 3, we briefly describe the technology of defect printability analysis based on process simulations. We will demonstrate that with the help of calibrated process simulations, we can quite accurately predict the printabilities of various test defects.

Improving resolution in photolithography with a phase-shifting mask

Abstract: The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Methods and systems for utilizing design data in combination with inspection data

Abstract: Various methods and systems for utilizing design data in combination with inspection data are provided. One computer-implemented method for binning defects detected on a wafer includes comparing portions of design data proximate positions of the defects in design data space. The method also includes determining if the design data in the portions is at least similar based on results of the comparing step. In addition, the method includes binning the defects in groups such that the portions of the design data proximate the positions of the defects in each of the groups are at least similar. The method further includes storing results of the binning step in a storage medium.

Limits of lithography

Abstract: Lithography technology has been one of the key enablers and drivers for the semiconductor industry for the past several decades. Improvements in lithography are responsible for roughly half of the improvement in cost per function in integrated circuit (IC) technology. The underlying reason for the driving force in semiconductor technology has been the ability to keep the cost for printing a silicon wafer roughly constant while dramatically increasing the number of transistors that can be printed per chip. ICs have always been printed optically with improvements in lens and imaging material technology along with decreases in wavelength used fueling the steady improvement of lithography technology. The end of optical lithography technology has been predicted by many and for many years. Many technologies have been proposed and developed to improve on the performance of optical lithography, but so far none has succeeded. This has been true largely because it has always been more economical to push incremental improvements in the existing optical technology rather than displace it with a new one. At some point in time, the costs for pushing optical lithography technology beyond previously conceived limits may exceed the cost of introducing new technologies. In this paper the author examines the limits of lithography and possible future technologies from both a technical and economic point of view.

Methods and systems for determining a position of inspection data in design data space

Abstract: Various methods and systems for determining a position of inspection data in design data space are provided. One computer-implemented method includes determining a centroid of an alignment target formed on a wafer using an image of the alignment target acquired by imaging the wafer. The method also includes aligning the centroid to a centroid of a geometrical shape describing the alignment target. In addition, the method includes assigning a design data space position of the centroid of the alignment target as a position of the centroid of the geometrical shape in the design data space. The method further includes determining a position of inspection data acquired for the wafer in the design data space based on the design data space position of the centroid of the alignment target.

Method of design and fabrication of integrated circuits using regular arrays and gratings

Abstract: A circuit fabrication and lithography process utilizes a mask including dense repetitive structures of features that result in a wide array of fine densely populated features on the exposed substrate film. Following this, a trimming procedure is performed to remove any unwanted fine patterned features providing multiple trimmed patterns on the substrate. An optional final step adds additional features as well as the interconnect features thus forming a circuit pattern. In this manner, all fine features may be generated using the exact same density of intensity patterns, and therefore, maximum consistency between features is established without the need for optical proximity correction. The secondary exposures are substantially independent from the initial dense-feature exposure in that the exposure of one set of features and the subsequent exposure of another set of features result in separate independent resist or masking layer reactions, thus minimizing corner rounding, line end shortening and other related spatial frequency effects and unwanted exposure memory effects.