Huirem Tarunkumar

Bio: Huirem Tarunkumar is an academic researcher from National Institute of Technology, Manipur. The author has contributed to research in topics: Nullor & Filter (video). The author has an hindex of 4, co-authored 8 publications receiving 44 citations.

An active inductor employing a new four terminal floating nullor transconductance amplifier (FTFNTA)

Abstract: In this scientific study, a new analog active building block named as four terminal floating nullor transconductance amplifier (FTFNTA) is implemented. The FTFNTA design offers a combined essence o...

A novel Schmitt trigger and its application using a single four terminal floating nullor (FTFN)

Abstract: In this research paper, a simple clock wise and counter clock wise Schmitt trigger employing single four terminal floating nullor (FTFN) with two external resistors is presented. The proposed Schmitt trigger avails CMOS based FTFN and it is extended for the application as a square and triangular wave generator, by adding an external capacitor to it. In addition, the proposed waveform generator provides independent tunability of amplitude of square wave by implementing the passive resistors using MOS transistors which make the circuit to be integrated fully. Finally, the verification of the proposed design is verified using PSPICE to justify the theoretical analysis. Also, post layout simulation and the experimental verification using commercially available current feedback operational amplifier named as ICAD844 based implementation for FTFN are included to confirm the reliability of the circuit.

A review on various multipliers designs in VLSI

Abstract: In this paper we are going to study Array multiplier, Wallace multiplier, Bypassing multiplier, Modified Booth multiplier, Vedic multiplier and Booth recorded Wallace tree multiplier which have been proposed by different researchers. When the study of the various multipliers have been performed, Array multiplier is found to have the largest delay and large power consumption while Booth encoded Wallace tree multiplier has the least delay though it also have a large area. We also realized that, with proper optimization the performance of the multipliers can be increased significantly, irrespective of the type. Temporal tilling method optimized array multiplier delay and power dissipation is found to increase by 50% and 30% respectively while using the partially guarded technique power consumption is reduced by 10–44% with 30–36% less area overhead. Booth recorded Wallace tree multiplier is found to be 67% faster than the Wallace tree multiplier, 53% faster than the Vedic multiplier, 22% faster than the radix 8 booth multipliers. We also study various optimization techniques for Wallace multiplier, bypassing multiplier, modified booth multiplier and Vedic multiplier.

Four Input Single Output based third order universal filter using Four Terminal Floating Nullor

Abstract: This paper presents a Four Input Single Output based third order universal filter that offers all five sections of filter frequency responses with some passive components using active block named as Four Terminal Floating Nullor (FTFN). The design schematic uses two number of Four Terminal Floating Nullor (FTFN) with three numbers of resistors and capacitors each. The proposed universal filter is realised with CMOS implementation of FTFN as well as Current Feedback Operational Amplifier (CFOA) namely IC AD844 for FTFN realisation. The viability of the universal filter circuit is justified with PSPICE simulation that includes both CMOS and AD844 based realization of FTFN. Also theoretical verification is well performed for the sustainability of the proposed circuit along with experimental verification by using IC AD844.

An autonomous chaotic and hyperchaotic oscillator using OTRA

Abstract: This research paper reports a novel design for third order chaotic and hyperchaotic oscillator with cubic nonlinearity using single operational trans-resistance amplifier (OTRA) and few passive elements. The key nonlinear dynamical characteristics in terms of sensitivity, divergence, equilibrium point and Lyapunov exponent are recorded in this literature. The operational activity of the proposed oscillator based on OTRA is integrated using 0.25 µm TSMC CMOS parameter. For the generation of hyperchaotic oscillator, an external capacitor is added to the third order chaotic oscillator. To justify the theoretical nonlinear dynamics of proposed chaotic oscillator, PSPICE simulation by using CMOS based OTRA and experimental investigation using IC AD844 based OTRA are well implemented.

Inductance Simulators and Their Application to the 4th Order Elliptic Lowpass Ladder Filter Using CMOS VD-DIBAs

Abstract: This paper presents inductance simulators using the voltage differencing differential input buffered amplifier (VD-DIBA) as an active building block. Three types of inductance simulators, including floating lossless inductance, series inductance-resistance, and parallel inductance-resistance simulators, are proposed, in addition to their application to the 4th order elliptic lowpass ladder filter. The simple design procedures of these inductance simulators using a circuit block diagram are also given. The proposed inductance simulators employ two VD-DIBAs and two passive elements. The complementary metal oxide semiconductor (CMOS) VD-DIBA used in this design utilizes the multiple-input metal oxide semiconductor (MOS) transistor technique in order to achieve a compact and simple structure with a minimum count of transistors. Thanks to this technique, the VD-DIBA offers high performances compared to the other CMOS structures presented in the literature. The CMOS VD-DIBAs and their applications are designed and simulated in the Cadence environment using a 0.18 µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). Using a supply voltage of ±0.9 V, the linear operation of VD-DIBA is obtained over a differential input range of −0.5 V to 0.5 V. The lowpass (LP) ladder filter realized with the proposed inductance simulators shows a dynamic range (DR) of 80 dB for a total harmonic distortion (THD) of 2% at 1 kHz and a 1.8 V peak-to-peak output. In addition, the experimental results of the floating inductance simulators and their applications are obtained by using VD-DIBA constructed from the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental ones, confirming the advantages of the inductance simulators and their application.

A fully/electronically controllable voltage-mode Schmitt trigger based on only single VDGA and its applications

Abstract: This article is objected to present a new fully/electronically controllable voltage-mode Schmitt trigger based on a modified voltage differencing gain amplifier (VDGA). It can offer both counterclockwise (CCW) and clockwise (CW) functions, without changing circuit topology. The proposed Schmitt trigger comprises merely one VDGA and three resistors. The hysteresis and amplitude of the output voltage of proposed Schmitt trigger can be independently controlled by corresponding bias currents of the VDGA. The modified VDGA was designed by a fully balanced differential transconductance technique based on 0.35 µm CMOS transistor technology, providing advantages in high gain, wide range of adjustability and symmetrical output signals. The performances of proposed Schmitt trigger were deeply investigated by not only simulation via PSpice program, but also experimental setup using commercially available integrated circuits. Both results agree well with the theoretical anticipation and are consistent each other. The total power consumption is approximately 1.39 mW at ± 1.5 V power supply. Additionally, to prove the practical use-abilities of the proposed Schmitt trigger, its applications in a voltage-mode relaxation oscillator, a triangular/square wave generator and a pulse width modulator are also included.

A novel Schmitt trigger and its application using a single four terminal floating nullor (FTFN)

Abstract: In this research paper, a simple clock wise and counter clock wise Schmitt trigger employing single four terminal floating nullor (FTFN) with two external resistors is presented. The proposed Schmitt trigger avails CMOS based FTFN and it is extended for the application as a square and triangular wave generator, by adding an external capacitor to it. In addition, the proposed waveform generator provides independent tunability of amplitude of square wave by implementing the passive resistors using MOS transistors which make the circuit to be integrated fully. Finally, the verification of the proposed design is verified using PSPICE to justify the theoretical analysis. Also, post layout simulation and the experimental verification using commercially available current feedback operational amplifier named as ICAD844 based implementation for FTFN are included to confirm the reliability of the circuit.