Non-rectangular transistors in today's advanced processes pose a potential problem between manufacturing and design as today's compact transistor models have only one length and one width parameter to describe the gate dimensions. The transistor model is the critical link between manufacturing and design and needs to account for across gate CD variation as corner rounding along with other 2D proximity effects become more pronounced. This is a complex problem as threshold voltage and leakage current have a very complex non-linear relationship with gate length. There have been efforts trying to model non-rectangular gates as transistors in parallel, but this approach suffers from the lack of accurate models for "slice transistors", which could potentially necessitate new circuit simulators with new sets of complex equations. This paper will propose a new approach that approximates a non-rectangular transistor with an equivalent rectangular transistor and hence does not require a new transistor model or significant changes to circuit simulators. Effective length extraction consists of breaking a non-rectangular transistor into rectangular slices and then taking a weighted average based on simulated slice currents in HSPICE. As long as a different effective length is used for delay and static power analysis, simulation results show that the equivalent rectangular transistor behaves the same as a non-rectangular transistor.

From poly line to transistor : Building BSIM models for non- rectangular transistors

Line/space dimensions for 32nm generation logic are expected to be ~45-50nm at ~90-100nm p itch. It is likely that the node will begin at the upper end of the range, and then shrink by ~10% to a 28nm node. For the lower end of the range, even with immersion scanners, the Rayleigh k 1 factor is below 0.32. The 22nm logic node should begin with minimum pitches of approximately 70nm, requiring some form of double patterning to maintain k 1 above 0.25. Logic patterning has been more difficult than NAND Flash patterning because random logic was designed with complete freedom compared to the very regular patterns used in memory. The logic layouts with bends and multiple pitches resulted in larger rules, un-optimized illumination, and a poorly understood process windows with little control of context-dependent hot spots.[1] The introduction of logic design styles which use strictly one-directional lines for the critical levels now gives the opportunity for illumination optimization. Gridded Design Rules (GDR) have been demonstrated to give area-competitive layouts at existing 90, 65, and 45nm logic nodes while reducing CD variability.[2] These benefits can be extended to  32nm logic using selective double pass patterning. Keywords: Low k

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32nm and below logic patterning using optimized illumination and double patterning

Non-ideal pattern transfer from drawn circuit layout to manufactured nanometer transistors can severely affect electrical characteristics such as drive current, leakage current, and threshold voltage Obtaining accurate electrical models of non-rectangular transistors due to sub-wavelength lithography effects is indispensable for DFM-aware nanometer IC design In this paper, TCAD device simulations are utilized to quantify the accuracy of a standard equivalent gate length extraction approach for non-rectangular transistors It is verified that threshold voltage and current density are non-uniform along the channel width due to narrow-width related edge effects, leading to significant inaccuracy in the sub-threshold region A new EGL extraction method utilizing location-dependent weighting factors and convex parameter extraction techniques is proposed to account for the current density non-uniformity Preliminary results verified by TCAD simulations indicate that the accuracy of leakage current estimation for non-rectangular transistors can be significantly improved The method is readily applicable to calibration with real silicon data

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A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects

Highly regular gridded designs have been generally accepted 1 as a key component for continued advances in lithographic resolution in an era of limited further progress in lithography hardware. With a given process technology tool set, higher pattern density (lower k1) and quality are achieved using gridded design rules (GDR) in comparison to conventional 2D designs. GDR is necessary for designs with k1 approaching the theoretical Rayleigh limit ~ 0:25. High pattern densities (fine pitch) and good image quality and manufacturability are achieved by very regular designs Fig. 1, which avoid complex corner structures and pattern density variations typical for conventional 2D designs. In particular lines+cuts implementations of GDR are well-suited for pitch splitting and multiple patterning, where the critical cuts patterns can be easily separated into groups with larger pitch for separate patterning. Very advanced technology nodes thus become possible with conventional lithography technology, see 2 for 11nm results.

Characterization of 1D layout technology at advanced nodes and low k1

In this work we present an application of a novel DFM (Design For Manufacturability) simulation flow, which self-consistently predicts the impact of the manufacturing process on electrical circuit behavior. We apply our methodology to the design of a 2x2 AND-OR standard cell to show its effectiveness. We show that process distortions significantly impact both DC and transient circuit-behavior, and have to be considered for accurate timing analysis, prediction of IDDQ and other circuit characteristics. Intrinsic process variability and process excursions cause additional deviation from design intent and therefore performance issues and potential yield losses. This work extends and generalizes concepts introduced in [1-2] and presents an integrated implementation of a self-consistent simulation flow [3] which provides unique insight into process-design interactions.

Integrated Simulation Flow for Self-Consistent Manufacturability and Circuit Performance Evaluation

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

Hung-Jen Lin

Papers

A novel design-process optimization technique based on self-consistent electrical performance evaluation