The development of computation technology and artificial intelligence (AI) field brings about AI to be applied to various system. In addition, the research on hardware-based AI processors leads to the minimization of AI devices. By adapting the AI device to the edge of internet of things (IoT), the system can perform AI operation promptly on the edge and reduce the workload of the system core. As the edge is influenced by the characteristics of the embedded system, implementing hardware which operates with low power in restricted resources on a processor is necessary. In this paper, we propose the intellino, a processor for embedded artificial intelligence. Intellino ensures low power operation based on optimized AI algorithms and reduces the workload of the system core through the hardware implementation of a neural network. In addition, intellino’s dedicated protocol helps the embedded system to enhance the performance. We measure intellino performance, achieving over 95% accuracy, and verify our proposal with an field programmable gate array (FPGA) prototyping.

Intellino: Processor for Embedded Artificial Intelligence

Topological indices are indispensable tools for analyzing networks to understand the underlying topology of these networks. Spiking neural network architecture (SpiNNaker or TSNN) is a million-core calculating engine which aims at simulating the behavior of aggregates of up to a billion neurons in real time. Tickysim is a timing-based simulator of the interchip interconnection network of the SpiNNaker architecture. Tickysim spiking neural network is considered to be highly symmetrical network classes. Classical degree-based topological properties of Tickysim spiking neural network have been recently determined. Ev-degree and ve-degree concepts are two novel degrees recently defined in graph theory. Ev-degree and ve-degree topological indices have been defined as parallel to their corresponding counterparts. In this study, we investigate the ev-degree and ve-degree topological properties of Tickysim spiking neural network. These calculations give the information about the underlying topology of Tickysim spiking neural network.

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On Ev-Degree and Ve-Degree Topological Properties of Tickysim Spiking Neural Network.

Low power Ti-doped NbO2-based selector device with high selectivity and low OFF current

The memristor-based convolutional neural network (CNN) gives full play to the advantages of memristive devices, such as low power consumption, high integration density, and strong network recognition capability. Consequently, it is very suitable for building a wearable embedded application system and has broad application prospects in image classification, speech recognition, and other fields. However, limited by the manufacturing process of memristive devices, high-precision weight devices are currently difficult to be applied in large-scale. In the same time, high-precision neuron activation function also further increases the complexity of network hardware implementation. In response to this, this paper proposes a configurable full-binary convolutional neural network (CFB-CNN) architecture, whose inputs, weights, and neurons are all binary values. The neurons are proportionally configured to two modes for different non-ideal situations. The architecture performance is verified based on the MNIST data set, and the influence of device yield and resistance fluctuations under different neuron configurations on network performance is also analyzed. The results show that the recognition accuracy of the 2-layer network is about 98.2%. When the yield rate is about 64% and the hidden neuron mode is configured as -1 and +1, namely ±1 MD, the CFB-CNN architecture achieves about 91.28% recognition accuracy. Whereas the resistance variation is about 26% and the hidden neuron mode configuration is 0 and 1, namely 01 MD, the CFB-CNN architecture gains about 93.43% recognition accuracy. Furthermore, memristors have been demonstrated as one of the most promising devices in neuromorphic computing for its synaptic plasticity. Therefore, the CFB-CNN architecture based on memristor is SNN-compatible, which is verified using the number of pulses to encode pixel values in this paper.

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Memristor Based Binary Convolutional Neural Network Architecture With Configurable Neurons.

The write operation of a resistive memory based on a one-selector–one-resistor (1S1R) crossbar array consumes significant energy and is dependent on the device and circuit characteristics as well as the bias scheme. In this paper, the energy efficiency of a crossbar array of a 1S1R configuration during a write operation is explored for the $V/2$ and $V/3$ bias schemes. The characteristics that affect the most energy-efficient bias scheme are demystified. The write energy of a crossbar array is modeled in terms of the array size, number of selected cells, and nonlinearity factor. For a specific array size and selector technology, the number of selected cells during a write operation can affect the choice of bias scheme. The effect of leakage current due to partially biased unselected cells is explored. Furthermore, an energy-efficient write operation based on a hybrid bias scheme is proposed to reduce the write energy. This write operation adaptively sets the bias scheme based on the number of selected cells to enhance overall energy efficiency. Energy improvements of more than two times are demonstrated with this hybrid bias scheme.

Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors

This paper proposes Full-Parallel Convolutional Neural Networks (FP-CNN) for specific target recognition, which utilize the analog memristive array circuits to carry out the vector-matrix multiplication, and generate multiple output feature maps in one single processing cycle. Compared with ReLU and Tanh function, we adopt the absolute activation function innovatively to reduce the network scale dramatically, which can achieve 99% recognition accuracy rate with only three layers. Furthermore, we propose a performance metrics function to resize the scale of the FP-CNN for solving different classification tasks. With the help of such design guidelines, the FP-CNN can still achieve over 96% recognition accuracy under the condition of 95% yield of memristor crossbar array and 0.5% Single-Pole-Double-Throw switches (SPDT) noise.

https://www.jstage.jst.go.jp/article/elex/16/3/16_16.20181034/_pdf

A memristor-based convolutional neural network with full parallelization architecture

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Quaternary synapses network for memristor-based spiking convolutional neural networks

Selector is indispensable to suppress leakage current for crossbar array of resistive random access memory. According to the nonlinear requirement, electron tunneling mechanism is firstly attempted. However, earlier studies discovered drawbacks of insufficient current density. This work aims at exploring the idealized characteristic of selector based on FowlerNordheim tunneling mechanism by selecting various materials and structures. Thereinto, current density transforms to drive voltage according to corresponding current density standard. Simulation results indicate that metal/insulator barrier and insulator thickness play key roles in determining drive voltage and nonlinearity of the tunneling selectors. Specifically, metal/insulator barrier influence drive voltage and nonlinearity, while insulator thickness mainly influence drive voltage. Thus it can help comprehend restrictions of tunneling mechanism and attempt other improvement directions.

https://www.jstage.jst.go.jp/article/elex/14/17/14_14.20170739/_pdf

Exploration of selector characteristic based on electron tunneling for RRAM array application

Frequency response mismatches (FRMs) in time-interleaved analog-to-digital converters (TIADCs) generate undesired spurs degrading the performance of TIADCs. This paper introduces a digital calibration method for the FRM in M-channel TIADCs (M-TIADCs). This method exploits fixed differentiator finite-impulse response (FIR) filters and the Hadamard transform to reconstruct the mismatch induced error signal. The mismatch parameters are estimated utilizing a short training signal and the least square (LS) method. Our method is simpler in terms of implementation compared with conventional methods as cumbersome time-varying filters, complex signal processing and front-end hardware modifications are avoided. Numerical simulation results demonstrate the efficacy and efficiency of the proposed method.

A calibration method for frequency response mismatches in M-channel time-interleaved analog-to-digital converters

The time-interleaved analog-to-digital converter (TIADC) is an architecture used to achieve a high sampling rate and high dynamic performance. However, estimation and compensation methods are required to maintain the dynamic performance of the constituent analog-to-digital converters (ADCs) due to channel mismatches. This paper proposes a blind adaptive method to calibrate the nonlinear mismatches in M-channel TIADCs (M-TIADCs). The nonlinearity-induced error signal is reconstructed by the proposed multiplier Hadamard transform (MHT) structure, and the nonlinear parameters are estimated by the filtered-X least-mean square (FxLMS) algorithm. The performance of cascade calibration is also analyzed. The numerical simulation results show that the proposed method consumes much less hardware resources while maintaining the calibration performance.

Husheng Liu

Papers

A memristor-based convolutional neural network with full parallelization architecture

Quaternary synapses network for memristor-based spiking convolutional neural networks

Exploration of selector characteristic based on electron tunneling for RRAM array application

A calibration method for frequency response mismatches in M-channel time-interleaved analog-to-digital converters

A Calibration Method for Nonlinear Mismatches in M-Channel Time-Interleaved Analog-to-Digital Converters Based on Hadamard Sequences