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Hyoung-Il Lee

Bio: Hyoung-Il Lee is an academic researcher from Seoul National University. The author has contributed to research in topics: Packet switching & Crossbar switch. The author has an hindex of 5, co-authored 18 publications receiving 104 citations. Previous affiliations of Hyoung-Il Lee include Electronics and Telecommunications Research Institute & Korean Intellectual Property Office.

Papers
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Patent
09 Jun 2003
TL;DR: In this article, a multiple input/output-queued (MIOQ) switch is presented, which comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress line; and m×M interconnection network each can move the arrived packet at output from the m ingress line to one or N) output buffer.
Abstract: A multiple input/output-queued(MIOQ) switch is presented. This MIOQ switch comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at each output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress lines; and m×M interconnection networks each of which is able to move the arrived packet at output from the m egress lines to one of the M(wherein M is m or N) output buffers. The multiple input/output-queued(MIOQ) switch according to the present invention requires no “speed-up”. Performance matches the performance of an output-queued switch.

23 citations

Journal ArticleDOI
TL;DR: The newly developed inside-out routing algorithm is shown to provide comparable degrees of freedom in realizing a given permutation as the well-known looping algorithm, while it can be more generally applied to a class of 2log/sub 2/N- or (2log/ sub 2/ N-1)-stage rearrangeable networks.
Abstract: In this paper, we analyze ways of realizing permutations in a class of 2log/sub 2/N- or (2log/sub 2/N-1)-stage rearrangeable networks. The analysis is based on the newly developed inside-out routing algorithm and we derive the upper and lower bounds on the number of possible realizations of a permutation. It is shown that the algorithm can provide us with comparable degrees of freedom in realizing a given permutation as the well-known looping algorithm, while it can be more generally applied to a class of 2log/sub 2/N- or (2log/sub 2/N-1)-stage rearrangeable networks. In finding a set of complete assignments for the center-stage cycles, alternate realizations of a permutation can be obtained by changing the initial position, changing the assigning direction, or even interchanging the first-level decompositions of the permutation. We also show that these numerable alternate realizations can be utilized to make the networks tolerate some sets of faults, i.e., control faults of SEs including stuck-at-straight and stuck-at-cross. Various cases of single control faults at the center stages and other stages are examined through examples. These new approaches originate from routing outward from center stages to outer stages; therefore, the center stages and two half networks may be treated separately.

14 citations

Proceedings ArticleDOI
11 Dec 2006
TL;DR: A novel load-balancing scheme for two-stage switches which does not disturb the sequence of packets and can achieve 100% throughput under not only uniform but also non-uniform traffic.
Abstract: In this paper, we propose a novel load-balancing scheme for two-stage switches which does not disturb the sequence of packets. The proposed scheme uses chamber queues(CQs) in front of the second crossbar fabric as well as VOQs in front of the first crossbar. A chamber queue is composed of N banks each of which can store only one packet destined for each output. The two crossbar fabrics in the proposed switch are configured by a deterministic sequence of N connection patterns as in other two-stage switches. In a time slot, the proposed switch transfers packets from non-empty VOQs to the corresponding empty banks of CQs via the first crossbar, and the packets from CQs are switched to their destinations via the second crossbar. While the proposed scheme is very simple, it can achieve 100% throughput under not only uniform but also non-uniform traffic. Moreover, the simulation results show that the average delay of packets in the proposed two-stage switch is lower than that in the original two-stage switch.

13 citations

Journal ArticleDOI
TL;DR: A novel load-balancing scheme for two-stage switches, which does not disturb the sequence of packets and can achieve 100% throughput under not only uniform but also non-uniform traffic.
Abstract: In this letter, we propose a novel load-balancing scheme for two-stage switches, which does not disturb the sequence of packets. The proposed scheme uses chamber queues (CQs) in front of the second crossbar fabric as well as VOQs in front of the first crossbar. While the proposed scheme is very simple, it can achieve 100% throughput under not only uniform but also non-uniform traffic. Moreover, the simulation results show that the average delay of packets in the proposed two-stage switch is lower than that of the original two-stage switch.

11 citations

Patent
09 Jun 2003
TL;DR: In this paper, a multiple input/output-queued (MIOQ) switch is presented, which comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress line; and m×M interconnection network each can move the arrived packet at output from the m ingress line to one or N) output buffer.
Abstract: A multiple input/output-queued(MIOQ) switch is presented. This MIOQ switch comprises a (k,m)-dimensional crossbar fabric having k ingress lines and m egress lines; N input buffers at each input; M output buffers at each output; N×k interconnection networks each of which is able to move a packet from each input to one of the k egress lines; and m×M interconnection networks each of which is able to move the arrived packet at output from the m egress lines to one of the M(wherein M is m or N) output buffers. The multiple input/output-queued(MIOQ) switch according to the present invention requires no “speed-up”. Performance matches the performance of an output-queued switch.

7 citations


Cited by
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Journal ArticleDOI
01 May 1975
TL;DR: The Fundamentals of Queueing Theory, Fourth Edition as discussed by the authors provides a comprehensive overview of simple and more advanced queuing models, with a self-contained presentation of key concepts and formulae.
Abstract: Praise for the Third Edition: "This is one of the best books available. Its excellent organizational structure allows quick reference to specific models and its clear presentation . . . solidifies the understanding of the concepts being presented."IIE Transactions on Operations EngineeringThoroughly revised and expanded to reflect the latest developments in the field, Fundamentals of Queueing Theory, Fourth Edition continues to present the basic statistical principles that are necessary to analyze the probabilistic nature of queues. Rather than presenting a narrow focus on the subject, this update illustrates the wide-reaching, fundamental concepts in queueing theory and its applications to diverse areas such as computer science, engineering, business, and operations research.This update takes a numerical approach to understanding and making probable estimations relating to queues, with a comprehensive outline of simple and more advanced queueing models. Newly featured topics of the Fourth Edition include:Retrial queuesApproximations for queueing networksNumerical inversion of transformsDetermining the appropriate number of servers to balance quality and cost of serviceEach chapter provides a self-contained presentation of key concepts and formulae, allowing readers to work with each section independently, while a summary table at the end of the book outlines the types of queues that have been discussed and their results. In addition, two new appendices have been added, discussing transforms and generating functions as well as the fundamentals of differential and difference equations. New examples are now included along with problems that incorporate QtsPlus software, which is freely available via the book's related Web site.With its accessible style and wealth of real-world examples, Fundamentals of Queueing Theory, Fourth Edition is an ideal book for courses on queueing theory at the upper-undergraduate and graduate levels. It is also a valuable resource for researchers and practitioners who analyze congestion in the fields of telecommunications, transportation, aviation, and management science.

2,562 citations

Patent
Edwin Rijpkema1, John Dielissen1
11 May 2006
TL;DR: In this article, an electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IPl - IP5) to enable a communication between the processing modules.
Abstract: An electronic device is provided which comprises an interconnect means (N) for coupling a plurality of processing modules (IPl - IP5) to enable a communication between the processing modules (IPl - IP5). The electronic device further comprises a plurality of network interfaces (NI) for coupling the interconnect means (N) to one of the processing modules (IPl - IP5). Furthermore, at least one time slot allocating unit (SA) is provided for allocating time slots to channels of the interconnect means (N). The time slot allocating unit (SA) comprises a plurality of slot tables (TO - T4) with a plurality of entries. Each entry corresponds to a fraction of the available bandwidth of the interconnect means (N). A first slot table of the plurality of slot tables (TO - T4) comprises at least one first entry of the plurality of entries which relates to a second slot table of the plurality of slot tables (TO - T4).

75 citations

Journal ArticleDOI
TL;DR: This paper presents several fast, practical linear-complexity scheduling algorithms that enable provision of various quality-of-service (QoS) guarantees in an input-queued switch with no speedup, and presents theoretical proofs and demonstrate by simulations that the edge weights are bounded.
Abstract: We present several fast, practical linear-complexity scheduling algorithms that enable provision of various quality-of-service (QoS) guarantees in an input-queued switch with no speedup. Specifically, our algorithms provide per-virtual-circuit transmission rate and cell delay guarantees using a credit-based bandwidth reservation scheme. Our algorithms also provide approximate max-min fair sharing of unreserved switch capacity. The novelties of our algorithms derive from judicious choices of edge weights in a bipartite matching problem. The edge weights are certain functions of the amount and waiting times of queued cells and credits received by a virtual circuit. By using a linear-complexity variation of the well-known stable-marriage matching algorithm, we present theoretical proofs and demonstrate by simulations that the edge weights are bounded. This implies various QoS guarantees or contracts about bandwidth allocations and cell delays. Network management can then provide these contracts to the clients. We present several different algorithms of varied complexity and performance (as measured by the usefulness of each algorithm's contract). While most of this paper is devoted to the study of "soft" guarantees, a few "hard" guarantees can also be proved rigorously for some of our algorithms. As can be expected, the provable guarantees are weaker than the observed performance bounds in simulations. Although our algorithms are designed for switches with no speedup, we also derive upper bounds on the minimal buffer requirement in the output queues necessary to prevent buffer overflow when our algorithms are used in switches with speedup larger than one.

61 citations

Patent
15 Nov 2004
TL;DR: In this paper, a high speed and high capacity switching apparatus is described, which includes: N input ports each of which for outputting maximum l cells in a time slot, wherein each of the n input ports includes N virtual output queues (VOQs) which are grouped in a group with n VOQs; N×N switch fabric having l 2 crossbar switch units for scheduling cells inputted from N input points based on a first arbitration function based on round-robin, wherein l VOQ groups are connected to l XSUs; and N output ports
Abstract: A high speed and high capacity switching apparatus is disclosed. The apparatus includes: N input ports each of which for outputting maximum l cells in a time slot, wherein each of the N input ports includes N virtual output queues (VOQs) which are grouped in l virtual output queues group with n VOQs; N×N switch fabric having l 2 crossbar switch units for scheduling cells inputted from N input ports based on a first arbitration function based on a round-robin, wherein l VOQ groups are connected to l XSUs; and N output ports connected to l XSUs for selecting one cell from l XSUs in a cell time slot by scheduling cells by a second arbitration function based on a backlog weighed round-robin, which operates independently of the first arbitration function, and transferring the selected cell to its output link.

61 citations

Patent
26 Jul 2004
TL;DR: In this article, a crosspoint matrix for communicatively connecting one of the input line cards to one of output line cards is proposed, where the switch device is capable of operating in either a cross-point mode for routing cells or packets from to a node to one node, or a scheduler mode for controlling flow of cells and packets through at least one other node.
Abstract: A network switching system includes transceiver devices respectively provided for a plurality of input line cards. The switching system also includes transceiver devices respective provided for a plurality of output line cards. The switching system further includes a switch device communicatively coupled to each o~ the plurality of input line cards and the plurality of output line cards. The switch device includes a crosspoint matrix for communicatively connecting one of the input line cards to one of the output line cards. The switch device is capable of operating in either a crosspoint mode for routing cells or packets from to one of the input line cards to one of the output line cards, or a scheduler mode for controlling flow of cells and/or packets through at least one other switch device.

52 citations