Hyun-Kook Park

Bio: Hyun-Kook Park is an academic researcher from Yonsei University. The author has contributed to research in topics: Static random-access memory & Process variation. The author has an hindex of 4, co-authored 7 publications receiving 68 citations.

FinFET SRAM Optimization With Fin Thickness and Surface Orientation

Abstract: In this paper, the design space, including fin thickness (Tfin), fin height (Hfin), fin ratio of bit-cell transistors, and surface orientation, is researched to optimize the stability, leakage current, array dynamic energy, and read/write delay of the FinFET SRAM under layout area constraints. The simulation results, which consider the variations of both Tfin and threshold voltage (Vth), show that most FinFET SRAM configurations achieve a superior read/write noise margin when compared with planar SRAMs. However, when two fins are used as pass gate transistors (PG) in FinFET SRAMs, enormous array dynamic energy is required due to the increased effective gate and drain capacitance. On the other hand, a FinFET SRAM with a one-fin PG in the (110) plane shows a smaller write noise margin than the planar SRAM. Thus, the one-fin PG in the (100) plane is suitable for FinFET SRAM design. The one-fin PG FinFET SRAM with Tfin = 10 nm and Hfin = 40 nm in the (100) plane achieves a three times larger noise margin when compared with the planar SRAM and consumes a 17% smaller bit-line toggling array energy at a cost of a 22% larger word-line toggling energy. It also achieves a 2.3 times smaller read delay and a 30% smaller write delay when compared with the planar SRAM.

Low-power 5t sram with improved stability and reduced bitcell size

Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM (400) includes a storage element (402) for storing data, wherein the storage element is coupled a first voltage and a ground voltage. The storage element can include symmetrically sized cross - coupled inverters. A single access transistor (M5 ) controls read and write operations on the storage element (402). Control logic (M6,M6') is configured to generate a value of the first voltage for a write operation that is different from the value of the first voltage for a read operation.

Accurate projection of V ccmin by modeling “dual slope” in FinFET based SRAM, and impact of long term reliability on end of life V ccmin

Abstract: Supply voltage (Vcc) scaling is mostly used method to achieve low power consumption. However, a high Vccmin is required to meet the high target yield because the SRAM yield according to Vcc scaling shows “dual slope”. In this paper, the root causes of “dual slope” are analyzed. Both side effect of SRAM bitcell on the yield is also considered to accurately project Vccmin, which results in 40mV increase of Vccmin to meet 99% target yield for 32nm HK/MG planar 1M SRAM. The “dual slope” effect on the yield is compared for 32nm HK/MG planar and FinFET 32M SRAMs with high (HD) and low doping (LD). Under the “dual slope” effect, the channel length adjustment method for pass gate transistor is proposed to reduce Vccmin of FinFET SRAM. When the number of finis is 1∶2∶2(=PU∶PG∶PD), HD and LD 32M FinFET SRAMs improve Vccmin by 370mV and 500mV, respectively, compared to 32M planar counterparts using the proposed the channel length adjustment method. Effect of NBTI and PBTI on Vccmin is also investigated. BTI degradation is greatly dependent on HK thickness and surface plane orientation of FinFET. End of Life (EOL) Vccmin optimization therefore requires careful selection of HK thickness and surface orientation.

Asymmetric Independent-Gate MOSFET SRAM for High Stability

Abstract: In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array architecture is also suggested to prevent read stability degradation in the half-selected cell, where word line is selected but bit line is unselected. The previous SRAMs with IG-MOSFET (IG-SRAMs) fail to simultaneously improve read stability and writeability compared to the SRAM with the tied-gate MOSFET. The proposed IG-SRAM significantly improves both read stability and writeability at the cost of slightly increased bit-cell area and read delay, as compared to the previous IG-SRAMs.

SRAM bitcell design for low voltage operation in deep submicron technologies

Abstract: As technology scales down, an increasing number of transistors can be integrated into a single chip but process variation becomes more serious. SRAM is one of the key components in a SoC and it occupies a large portion of the SoC. Thus, the SRAM bitcell is typically designed using very small transistors for high integration, which limits the minimum operating voltage (V CCmin ) of the SoC because of the large threshold voltage (V th ) mismatch between paired transistors caused by small feature size. As process technology scales down to sub-32nm technology, the 6T SRAM bitcell that is currently used may not achieve proper stability, write-ability, and read-ability at the required operating voltage. In this paper, several approaches are investigated to resolve the issue, such as upsized 6T SRAM bitcell, 8T SRAM bitcell, read- and write-preferred bitcells, and read- and write-assist circuits. HSPICE simulations are performed using PTM 32nm model parameters.

FinFETs: From Devices to Architectures

Abstract: Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.

Smart mobile SoCs driving the semiconductor industry: Technology trend, challenges and opportunities

Abstract: The explosive growth of smart mobile wireless devices in recent years has fundamentally transformed the semiconductor industry. Mobile system-on-chips (SoCs) has become the leading product driver for technology definition and manufacturing for the semiconductor industry. This trend was first observed in 28 nm and will continue for 20 nm, 16/14 nm, and 10 nm adoption and production ramp. Recent mobile SoC performance increase was achieved mainly through silicon technology scaling, and from single to dual- and quad-core. For mobile SoCs to continue offering new and exciting user-experiences, and longer battery life, a holistic approach in orthogonal system scaling to break out of the box of (speed*density/power/cost) constrains is mandated. Examples in the new paradigm of mobile heterogeneous computing are: energy-efficient transistors/memories/interconnects in expanding and boosting existing SoC functionalities (e.g., SiGe/III-V FinFET, GAA-FET, TFET, and RRAM/MRAM etc.), all-inclusive technology/design co-optimization to extract more values from silicon tech, RFFE system integration, and the multi-die integration by system partitioning that allows each component to be optimized and integrated closely together for lower cost and power, higher performance, and reduced form factor. Numerous challenges are ahead yet tremendous opportunities exist for collaborative and multiplicative innovations in the industry to enable the continued growth of mobile SoCs.

Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design

Abstract: Space applications demand highly stable and reliable SRAM circuits for secure and the uninterrupted operation. In this paper, we propose advanced FinFET and self-refreshing logic-based 12T SRAM cell (WWL12T). The dual- ${k}$ gate insulator and symmetric spacer are used to improve the reliability and performance of the FinFET. The outer side high- ${k}$ insulator reduces the charge trapping to the gate oxide and improves the ON current along with reduced short channel effects. WWL12T uses extra word line for bit interleaving aware design and a feedback circuit for stable space applications. In the read operation, the extra ${P}$ -type transistors are active according to the stored data bits and charge the storing nodes using bit-line voltages. The static noise margin and word line write margin of proposed WWL12T SRAM cell under worst case process variation and single charge trapping improve by 6.4% and 8.4%, respectively compared to existing 12T SRAM.

Modeling study on carrier mobility in ultra-thin body FinFETs with circuit-level implications

Abstract: Influence of fin width downscaling on hole and electron mobility behavior in FinFETs with (1 0 0), (1 1 0) and (1 1 1) oriented sidewalls is examined. Our effective-mass model reproduces experimental results of UTB SOI pMOSFETs fabricated on (1 0 0) and (1 1 0) surfaces, including the effect of mobility enhancement for certain body thicknesses in (1 1 0) oriented devices. The suitability of well-calibrated EMA for the simulation of hole mobility is confirmed by our results, which opens a possibility of using hole EMA in advanced Monte Carlo simulators. Simulations show that with the downscaling of fin width nFinFETs with (1 0 0) sidewalls and pFinFETs with (1 1 0) and (1 1 1) sidewalls exhibit mobility enhancement in certain fin-width ranges. In contrast, other FinFET configurations experience monotonic mobility degradation with the decreasing fin width. Regarding experimental (1 1 1) FinFETs from our previous work, modeling results suggest that the fin width is highly uniform along the channel, both in nFinFETs and pFinFETs. The impact of electron and hole mobility behavior in UTB FinFETs on SRAM design is also studied. We have found that FinFETs with (1 1 1) active surface enable the most efficient use of the layout area, demanding only four fins for an SRAM cell with matched inverters and high immunity to noise.