Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.

Transistors with high concentration of boron doped germanium

Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Contact resistance reduction employing germanium overlayer pre-contact metalization

Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.

Column iv transistors for pmos integration

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Reflection electron energy loss spectroscopy for ultrathin gate oxide materials

The band alignment of atomic layer deposited (HfZrO4)1−x(SiO2)x (x = 0, 0.10, 0.15, and 0.20) gate dielectric thin films grown on Si (100) was obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence band offset, and conduction band offset values for HfZrO4 silicate increased from 5.4 eV to 5.8 eV, from 2.5 eV to 2.75 eV, and from 1.78 eV to 1.93 eV, respectively, as the mole fraction (x) of SiO2 increased from 0.1 to 0.2. This increase in the conduction band and valence band offsets, as a function of increasing SiO2 mole fraction, decreased the gate leakage current density. As a result, HfZrO4 silicate thin films were found to be better for advanced gate stack applications because they had adequate band gaps to ensure sufficient conduction band offsets and valence band offsets to Si.

Band alignment of atomic layer deposited (ZrO2)x(SiO2)1−x gate dielectrics on Si (100)

The $\mathrm{Ba}/\mathrm{Si}(111)$ surface, previously known as a $3\ifmmode\times\else\texttimes\fi{}1$ phase, is found to have a $3\ifmmode\times\else\texttimes\fi{}2$ periodicity and a semiconducting band gap. The substrate reconstructs into the honeycomb chain-channel (HCC) structure with Ba atoms in the channel, as in the alkali-metal-induced $\mathrm{Si}(111)\ensuremath{-}(3\ifmmode\times\else\texttimes\fi{}1)$. However, the metal coverage is determined to be 1/6 monolayers, half the alkali-metal coverage. We propose that the structure and the metal coverage determined for the Ba adsorbate is universal for other alkaline-earth-metal adsorbates. With the alkali-metal-induced $3\ifmmode\times\else\texttimes\fi{}1$ case, our results lead to a rule that one donated electron per $3\ifmmode\times\else\texttimes\fi{}1$ surface unit is necessary to stabilize the HCC reconstruction of Si.

Structure of the Ba-Induced Si(111)-(3 × 2) Reconstruction

We report on the absolute measurement of In coverage on the Si(111)4\ifmmode\times\else\texttimes\fi{}1-In surface using medium-energy ion scattering, and present bias-dependent scanning tunneling microscopy (STM) images. The In coverage was determined to be 1 monolayer (ML). This result is in contrast to previous results of 3/4-ML In determined by semidirect measurements using Auger electron spectroscopy and STM. Our result supports a 4\ifmmode\times\else\texttimes\fi{}1-In structural model consisting of four surface In rows, which was constructed from the recent surface x-ray diffraction study and tested by subsequent theoretical calculations. The bias-dependent STM images are well reproduced by ab initio simulations based on this 1-ML-In model.

Absolute In coverage and bias-dependent STM images of the Si(111)4×1-In surface

Methods of manufacturing semiconductor devices may include forming a first layer on a first active region (P-channel FET), forming a second layer on a second active region (N-channel FET), the first and second layers including a silicon germanium (SiGe) epitaxial layer sequentially stacked on a silicon (Si) epitaxial layer, forming a first contact hole in an interlayer insulating film including a first lower region exposing the SiGe epitaxial layer of the first layer, forming a second contact hole in the interlayer insulating film including a second lower region penetrating through the SiGe epitaxial layer of the second layer and exposing the Si epitaxial layer of the second layer, forming a first metal silicide film including germanium (Ge) in the first lower region, forming a second metal silicide film not including Ge in the second lower region simultaneously with the forming of the first metal silicide film.

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

The in-depth concentration of Ar atoms in Si surface after Ar + ion sputtering was investigated using medium-energy ion spectroscopy (MEIS) and dynamic Monte Carlo simulation. The primary Ar + ion energy was 0.5, 1 and 3 keV, and the primary Ar + ion beam direction was varied from surface normal to glancing angle. In the case of the surface normal incidence, the MEIS result shows that the maximum atomic concentration of Ar atoms increases from 6% at the depth of 2 nm to 16% at the depth of 3 nm as the primary ion energy increases from 0.5 to 3 keV. However, in the case of the incident angle of 80°, that is 2.5% at the depth of 1.5 nm when the primary energy is 3 keV, in-depth Ar distribution cannot be observable when the primary ion energy is 0.5 keV. Dynamic Monte Carlo simulation reproduced the in-depth concentration distribution of Ar atoms quantitatively.

Hyung-Ik Lee

Papers

Band alignment of atomic layer deposited (ZrO2)x(SiO2)1−x gate dielectrics on Si (100)

Structure of the Ba-Induced Si(111)-(3 × 2) Reconstruction

Absolute In coverage and bias-dependent STM images of the Si(111)4×1-In surface

Methods of manufacturing semiconductor devices with Si and SiGe epitaxial layers

In-depth concentration distribution of Ar in Si surface after low-energy Ar+ ion sputtering