Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.

The future of wires

The potential impact of high-/spl kappa/ gate dielectrics on device short-channel performance is studied over a wide range of dielectric permittivities using a two-dimensional (2-D) simulator implemented with quantum mechanical models. It is found that the short-channel performance degradation is caused by the fringing fields from the gate to the source/drain regions. These fringing fields in the source/drain regions further induce electric fields from the source/drain to channel which weakens the gate control. The gate dielectric thickness-to-length aspect ratio is a proper parameter to quantify the percentage of the fringing field and thus the short channel performance degradation. In addition, the gate stack architecture plays an important role in the determination of the device short-channel performance degradation. Using double-layer gate stack structures and low-/spl kappa/ dielectric as spacer materials can well confine the electric fields within the channel thereby minimizing short-channel performance degradation. The introduction of a metal gate not only eliminates the poly gate depletion effect, but also improves short-channel performance. Several approaches have been proposed to adjust the proper threshold voltage when midgap materials or metal gates are used.

The impact of high-/spl kappa/ gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs

This paper reports a full CMOS process using a combination of a TiN/W Metal Replacement Gate Transistor design with a high dielectric constant gate insulator of tantalum pentoxide over thin remote plasma nitrided gate oxide. MOS devices with high gate capacitances equivalent to that for <2 nm SiO/sub 2/ but having relatively low gate leakage are reported. Transistors with gate lengths near or below 0.1 /spl mu/m have good characteristics. Working CMOS circuits using Ta/sub 2/O/sub 5/ gate insulator are demonstrated for the first time.

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

An MOS-type semiconductor device comprises two semiconductors separated by an insulator. The two semiconductors comprise monocrystal semiconductors, each having a crystallographic orientation with respect to the insulator (or other crystallographic/semiconductor property) different to the crystallographic orientation (or other respective property) of the other semiconductor. This arrangement of crystallographic orientations (and other crystallographic/semiconductor properties) can yield reduced unintended electron tunneling or current leakage through the insulator vis a vis a semiconductor device in which such an arrangement is not used. Methods for forming the MOS-type semiconductor devices of the invention are also provided.

MOS-type semiconductor device and method for making same

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Improvement of threshold voltage deviation in damascene metal gate transistors

Summary form only given. Advances in lithography and thinner SiO/sub 2/ gate oxides have enabled the scaling of MOS (metal-oxide-semiconductor) technologies to sub-0.25 /spl mu/m feature size. High dielectric constant materials, such as Ta/sub 2/O/sub 5/, have been suggested as a substitute for SiO/sub 2/ as the gate material beyond t/sub ox/=25 /spl Aring/. However, the Si-Ta/sub 2/O/sub 5/ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. We present a solution to these issues through the synthesis of a SiO/sub 2/-Ta/sub 2/O/sub 5/-SiO/sub 2/ stacked dielectric. The fabricated transistors exhibit excellent I-V characteristics.

I.C. Kizilyaili

Papers

Stacked gate dielectrics with TaO for future CMOS technologies