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Author

I. G. Naveen

Bio: I. G. Naveen is an academic researcher. The author has contributed to research in topics: Literature survey & CMOS. The author has an hindex of 1, co-authored 1 publications receiving 2 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2016
TL;DR: A 10-bit low power SAR ADC which is simulated in 180nm CMOS technology and dynamic latch comparator is used to increase in speed of operation and to get lower power consumption.
Abstract: Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power consumption is attained by using Capacitive DAC. Capacitive DAC also incorporate Sample-and-Hold circuit in it. Dynamic latch comparator is used to increase in speed of operation and to get lower power consumption.

6 citations

Proceedings ArticleDOI
20 Nov 2022
TL;DR: In this article , the authors demonstrate how to use an ESP32-CAM module and a few electronic sensors to build a clever military robot to monitor border regions in a real-time computer vision workload.
Abstract: Robots are designed to carry out specialised tasks that humans are unable to do or in hazardous environments where human labour is not guaranteed. As a result, these kinds of vehicles can carry out tasks that are challenging for humans. Allowing a soldier the responsibility of surveillance in such circumstances is challenging since it could endanger the soldier's life. Instead, we can utilise a robot to monitor border regions. In this project, we'll demonstrate how to use an ESP32-CAM module and a few electronic sensors to build a clever military robot. Although the ESP32-CAM is a low power and low latency video streaming module and has GPIOs and serial connection, it does not appear powerful enough to handle some demanding real-time computer vision workloads.

Cited by
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Journal ArticleDOI
29 Jun 2021
TL;DR: A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSats-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design.
Abstract: The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

1 citations

Proceedings ArticleDOI
01 Jan 2019
TL;DR: The proposed ultra low energy reduced switching (RS) architecture for DAC employs a new charge sharing and restoration technique for generating the desired voltage and reduces the energy consumption for capacitor charging by 99.85%.
Abstract: This paper presents a novel architecture for a low energy Digital-to-Analog converter (DAC) used in Successive Approximation Register Analog-to-Digital converters (SAR ADCs). The proposed ultra low energy reduced switching (RS) architecture for DAC employs a new charge sharing and restoration technique for generating the desired voltage. Using its unique capacitor array and switching technique, it reduces the energy consumption for capacitor charging by 99.85% (for 10-bit) as compared to conventional SAR ADC. The proposed architecture requires a fewer number of switches as compared to other low energy architectures and efficiently reduces the switching energy as well.

1 citations

Proceedings ArticleDOI
05 Jul 2022
TL;DR: This paper presents a design of low power 8 bit 200KS/s Synchronous Successive Approximation Register analog to digital (SAR ADC) converter composed of Input Buffer, Dynamic Latch Comparator, Capacitive DAC, Reference Voltage Generator, and SAR Logic.
Abstract: This paper presents a design of low power 8 bit 200KS/s Synchronous Successive Approximation Register analog to digital (SAR ADC) converter. The proposed architecture is composed of Input Buffer, Dynamic Latch Comparator, Capacitive DAC, Reference Voltage Generator, and SAR Logic. Dynamic latch comparator is used to reduce the leakage current. In order to implement low power, the architecture of SAR ADC has been used and medium resolution among the architectures. The proposed structure is designed using 55-nm Complementary Metal-Oxided-Semiconductor (CMOS) process technology with 1V of supply voltage and 781.2 Hz of input frequency. The results of the architecture are achieved an effective number of bits (ENOB) of 7.997 bits and a signal to noise, distortion ration (SNDR) level of 49.899 dB with sampling rate 200KS/s. Furthermore, total power consumption of the structure is 245 uW.
Proceedings ArticleDOI
17 Mar 2023
TL;DR: In this article , a new logic ("D Logic") has been proposed which reduces the number of transistors required to implement the SAR logic by 18.53%, as well as power dissipation.
Abstract: The need for battery powered wearable gadgets has risen dramatically as the healthcare system has progressed. Unfortunately, these bio-medical signals are analog in nature and needs to be transformed to digital form before further processing. In a bio-medical sensor system, the bio-medical signal is first given to an analog front-end to raise signal amplitude and pre-process it. Later, it is converted in digital form to make use of digital signal processors (DSPs) with the help of analog to digital converter (ADC). One of the main blocks of ADC is SAR logic which uses D flip flops for realization. In this paper, a new logic ("D Logic") has been proposed which reduces the number of transistors required to implement the SAR logic by 18.53%, as well as power dissipation. The 10-bit ADC has been designed in 90 nm CMOS process using Cadence Virtuoso. The overall power consumption of the proposed SAR ADC is 67.53 µW.
Proceedings ArticleDOI
16 Oct 2022
TL;DR: In this paper , the authors presented a 12-bit ADC with 2 Transistor MUX and 10 Transistor Full adders (12B-2TM-10TFA) and their encoder was executed in Cadence Virtuoso 45 nm CMOS (Complementary Metal Oxide Semiconductor).
Abstract: High-performance Integrated Analog-to-Digital Converters (ADCs) are considered an essential part of Digital Signal Processing (DSP) and Microcontroller which connect both analog and digital systems. Furthermore, combining the Successive Approximation Register (SAR) with ADC has attained additional attention in terms of its digital responsiveness and power efficiency. As a result, DSP and Microcontrollers are used globally in electronic products such as biometric sensors and medical equipment. This paper presents a 12-Bit Analog to Digital Converter (ADC) and its encoder is designed with 2 Transistor MUX and 10 Transistor Full adders (12B-2TM-10TFA). The presented design is executed in Cadence Virtuoso 45 nm CMOS (Complementary Metal Oxide Semiconductor) technology. Furthermore, WL (Width/Length) ratio is considered as 2 for designing the full adder. For N-Channel Metal Oxide Semiconductor (NMOS), the width is considered as 120 nm, while for Positive-Channel Metal Oxide Semiconductor (PMOS) is considered as 240 nm, so it can produce better results while designing the proposed 10-T Full Adder. The performance measurements of proposed designs are calculated through power, area, current, and delay and the simulation results displayed that the proposed 12B-2TM-10TFA architecture reduced 39.59% of power, 9.8 % of the area, 18.42% of delay, and 33.39 % of current when compared to the existing folding flash ADC.