I. Hariharan

Bio: I. Hariharan is an academic researcher from Anna University. The author has contributed to research in topics: Control reconfiguration & Instruction prefetch. The author has an hindex of 1, co-authored 3 publications receiving 3 citations.

Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems

Abstract: Modern embedded systems are packed with dedicated Field Programmable Gate Arrays (FPGAs) to accelerate the overall system performance. However, the FPGAs are susceptible to reconfiguration overhead...

Algorithms for reducing reconfiguration overheads using prefetch, reuse, and optimal mapping of tasks

Abstract: Field Programmable Gate Arrays (FPGAs) are preferred in the modern embedded system to accelerate the performance of the entire system. However, the FPGAs are liable to suffer from reconfiguration overheads. These overheads are mainly because of the configuration data being fetched from the off‐chip memory at run‐time and due to the improper management of tasks during execution. To reduce these overheads, two algorithms are proposed. Both the algorithms focus on the prefetch heuristics, reuse technique, and an optimal mapping of tasks over the available memories. However, in terms of reusing technique, algorithm‐1 uses least recently used (LRU) policy and algorithm‐2 uses the optimal replacement policy (considering the vitality of the reconfigurable units (RUs)). Simulation results are obtained for both the algorithms. It is evident from the result that most of the reconfiguration overheads are eliminated when the applications are managed and executed based on the proposed algorithms. Also, the two algorithm results are compared and analyzed. For this purpose, the experiments included smaller and larger task graphs. In the case of smaller task graphs, algorithm‐2 outperforms algorithm‐1 in reducing reconfiguration overheads. In larger task graphs, algorithm‐1 produces better results compared to algorithm‐2.

Reducing Reconfiguration Overheads Using Configuration Prefetch, Optimal Reuse, and Optimal Memory Mapping

Abstract: Modern embedded systems are packed with dedicated field-programmable gate arrays (FPGAs) to accelerate the overall system performance. But the main drawback in using FPGA as a reconfigurable system is that a lot of reconfiguration overheads are generated in the reconfiguration process. The reconfiguration overheads are mainly because of the configuration data being fetched from the off-chip memory and also due to the improper management of tasks during execution. This work focusses mainly on the prefetch heuristics, reuse technique, and the available memory hierarchy to provide an efficient management of tasks over the available resources. This short communication proposes a new optimal replacement policy which reduces the overall time and energy reconfiguration overheads for static systems in their subsequent iterations. It is evident from the results that most of the time and energy reconfiguration overheads are eliminated.

A prefetch-aware scheduling for FPGA-based multi-task graph systems

Abstract: In partially run-time reconfigurable (PRR) FPGAs, hardware tasks should be configured before their execution. The configuration delay imposed by the reconfiguration process increases the total execution time of the hardware tasks and task graphs. In this paper, a new technique named forefront-fetch is presented to improve the makespan of hardware task graphs running on PRR FPGAs via alleviating the adverse effects of the configuration delays. In this technique, which is applied to a sequence of task graphs, the configuration of some tasks is carried out within the execution phase of the previous task graph. This strategy leads to hide the configuration delay of the forefront-fetched tasks that as a result improves the execution time. The proposed solution modifies the schedules of the task graphs at design time to obtain a set of schedule pairs for the run-time environment. Experiments on actual and synthesized task graphs demonstrate the ability of the proposed technique in improving the makespan of hardware task graphs. The obtained results show that for a set of task graphs running on Xilinx™ Virtex-5 XUPV5LX110T FPGA, makespan is improved by 37.81% on average. Moreover, the proposed solution outperforms state-of-the-art prefetch-aware scheduling strategies by 14.78% makespan improvement.

An Application Specific Reconfigurable Architecture with Reduced Area and Static Memory Cells

Abstract: An Application Specific Inflexible FPGA (ASIF) is a tailored design, for a given group of known circuits, which is generated by extensively reducing the routing resources of an FPGA. In an ASIF, di...

A Survey: FPGA-Based Dynamic Scheduling of Hardware Tasks

Abstract: To meet the increasing computing needs of various application fields, Field programmable gate array (FPGA) has been widely deployed. In FPGA-based processing, hardware tasks can be better accelerated by allocating appropriate computing resources. Therefore, FPGA-based hardware task scheduling has become one of the mainstream research directions in academia and industry. However, the optimization objectives of existing FPGA-based hardware task scheduling methods are relatively scattered. In this regard, this paper summarizes the research status of hardware task dynamic scheduling from the three essential elements of FPGA processing:time, resources, and power consumption. This paper analyzes, sorts out, categorizes the ideas and implementations of various scheduling methods and analyzes and evaluates optimization effects of various scheduling methods from multiple dimensions. Then, the shortcomings of the existing methods are summarized and some practical applications are introduced. Finally, the research direction of task scheduling based on FPGA is prospected and summarized.