I.J. Dedic

Bio: I.J. Dedic is an academic researcher from Fujitsu. The author has contributed to research in topics: CMOS & Switched capacitor. The author has an hindex of 2, co-authored 3 publications receiving 28 citations.

A sixth-order triple-loop sigma-delta CMOS ADC with 90 dB SNR and 100 kHz bandwidth

Abstract: The conversion rate of high-resolution wideband sigma-delta ADCs is limited by need for high oversampling ratio, typically 64 or more, for rejection of quantization noise. These rates lead to high amplifier power, large power-hungry digital filters, and difficult-to-drive signal and reference inputs. For 16b performance with low oversampling ratio it is necessary to use high-order noise shaping and/or multi-level quantizers and DACs, both leading to problems in design or manufacture if realized directly. The ADC described here consists of three cascaded second-order three-level loops giving a sixth-order noise-shaping function without linearity and stability problems from component mismatch or quantizer overload. >

A 16 bit 500ks/s 2.7V 5mW ADC/DAC in 0.8um CMOS using error-correcting successive approximation

Abstract: An embedded 16 bit ADC/DAC for an analogue signal processor uses error-correcting successive approximation to increase speed by relaxing settling time requirements. Using a low power switched capacitor/resistor shared DAC, it can perform simultaneous A/D and D/A conversion at 500ks/s using 5mW at 2.7V and occupies 2mm2in 0.8µm CMOS.

A 16 b 100 k sample/s 2.7 V 25 mW ADC/DSP/DAC-based analog signal processor in 0.8 /spl mu/m CMOS

Abstract: The 0.8/spl mu/m CMOS signal processor described combines a low-noise analog front-end and reference, 16b ADC/DAC, and 16b DSP optimized for filter applications. With 25mW typical power consumption at 100kSample/s (3mW for ADC/DAC) it can be programmed for high-order analog filtering and other signal processing functions with 80dB typical SNR.

An overview of sigma-delta converters

Abstract: Using sigma-delta A/D methods, high resolution can be obtained for only low to medium signal bandwidths. This article describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. We examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

Delta-Sigma modulator based A/D conversion without oversampling

Abstract: Although /spl Delta//spl Sigma/ modulators are widely used for low to moderate rate analog-to-digital conversion, the time oversampling requirement has discouraged their application to higher rate converters. This paper presents an architecture wherein multiple /spl Delta//spl Sigma/ modulators are combined so that neither time oversampling nor time interlacing are necessary. Instead, the system achieves the effect of oversampling from the multiplicity of modulators. For a system containing M P/sup th/-order /spl Delta//spl Sigma/ modulators, approximately P bits of accuracy are gained for every doubling of M. A major benefit of the architecture is that it retains much of the robustness of the individual /spl Delta//spl Sigma/ modulators to nonideal circuit behavior. As a result, the architecture offers the potential of integrating high-precision, high-speed A/D converters together with digital signal processing functions using VLSI processes optimized for digital circuitry. The paper presents the general architecture and provides a performance analysis closely supported by computer simulations.

An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution

Abstract: This article briefly describes conventional A/D conversion, as well as its performance modeling. We then look at the technique of oversampling, which can be used to improve the resolution of classical A/D methods. We discuss how sigma-delta converters use the technique of noise shaping in addition to oversampling to allow high resolution conversion of relatively low bandwidth signals. Next, we examine the use of sigma-delta converters to convert narrowband bandpass signals with high resolution. Several parallel sigma-delta converters, which offer the potential of extending high resolution conversion to signals with higher bandwidths, are also described.

Oversampling parallel delta-sigma modulator A/D conversion

Abstract: Conventional delta-sigma analog-to-digital converters (/spl Delta//spl Sigma/ADC's) are widely used in low-bandwidth applications such as high-fidelity audio processing because they offer high-precision conversion yet are amenable to implementation using fine-line VLSI processes optimized for digital circuitry. However, their oversampling requirement so far has prevented their widespread application to higher bandwidth applications such as video processing. This paper extends a recently developed delta-sigma ADC architecture called the pi-delta-sigma ADC (/spl Pi//spl Delta//spl Sigma/ADC) that consists of multiple /spl Delta//spl Sigma/ modulator channels operating in parallel without time-interleaving. The extension developed in this paper allows for oversampling to be combined with parallelism such that an M-channel system with an oversampling ratio of N can achieve a conversion performance close to that of a conventional /spl Delta//spl Sigma/ADC with an oversampling ratio of M/spl times/N. Thus, for a given conversion precision, the architecture offers relaxed oversampling relative to conventional /spl Delta//spl Sigma/ADCs in return for increased analog circuit area. Moreover, as will be shown, the /spl Pi//spl Delta//spl Sigma/ADC retains much of the robustness of conventional /spl Delta//spl Sigma/ADC's with respect to nonideal circuit behavior.

A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications

Abstract: A 13-bit, 1.4-MS/s, sixth-order cascaded sigma-delta modulator oversampling at 16 X is implemented in a 0.72 /spl mu/m complementary metal-oxide-semiconductor process for use in the baseband path of a radio-frequency receiver. The modulator achieves 77 dB of dynamic range and dissipates 81 mW from a 3.3 V supply. It is characterized for the blocking and intermodulation requirements of a cordless telephone application.