I
Ian R. Post
Researcher at Intel
Publications - 37
Citations - 1933
Ian R. Post is an academic researcher from Intel. The author has contributed to research in topics: Transistor & CMOS. The author has an hindex of 18, co-authored 37 publications receiving 1830 citations.
Papers
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Proceedings ArticleDOI
A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors
C. Auth,C. Allen,A. Blattner,Daniel B. Bergstrom,Mark R. Brazier,M. Bost,M. Buehler,V. Chikarmane,Tahir Ghani,Timothy E. Glassman,R. Grover,W. Han,D. Hanken,Michael L. Hattendorf,P. Hentges,R. Heussner,J. Hicks,D. Ingerly,Pulkit Jain,S. Jaloviar,Robert James,David Jones,J. Jopling,Subhash M. Joshi,C. Kenyon,Huichu Liu,R. McFadden,B. McIntyre,J. Neirynck,C. Parker,L. Pipes,Ian R. Post,S. Pradhan,M. Prince,S. Ramey,T. Reynolds,J. Roesler,J. Sandford,J. Seiple,Pete Smith,Christopher D. Thomas,D. Towner,T. Troeger,Cory E. Weber,P. Yashar,K. Zawadzki,Kaizad Mistry +46 more
TL;DR: In this paper, a 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time, which provides steep sub-threshold slopes (∼70mV/dec) and very low DIBL ( ∼50m V/V).
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Patent
Thin tensile layers in shallow trench isolation and method of making same
Kelin J. Kuhn,Ian R. Post +1 more
TL;DR: In this article, a method of forming an isolation trench that comprises forming a recess in a substrate and forming a film upon the sidewall under conditions that cause the film to have a tensile load was proposed.
Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Proceedings ArticleDOI
A high performance 180 nm generation logic technology
Simon Yang,S. Ahmed,B. Arcot,R. Arghavani,P. Bai,S. Chambers,P. Charvat,Raymond E. Cotner,R. Gasser,Tahir Ghani,Makarem A. Hussein,Chia-Hong Jan,C. Kardas,J. Maiz,P. McGregor,B. McIntyre,P. Nguyen,Paul A. Packan,Ian R. Post,Swaminathan Sivakumar,Joseph M. Steigerwald,M. Taylor,B. Tufts,S. Tyagi,M. Bohr +24 more
TL;DR: In this article, a 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low/spl epsi/ SiOF dielectrics.