Ichiro Omura

Bio: Ichiro Omura is an academic researcher from Kyushu Institute of Technology. The author has contributed to research in topics: Power semiconductor device & Insulated-gate bipolar transistor. The author has an hindex of 20, co-authored 147 publications receiving 2329 citations. Previous affiliations of Ichiro Omura include Toshiba & Xi'an Jiaotong University.

Power semiconductor device

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Method of manufacturing semiconductor device

Abstract: A method of manufacturing a semiconductor device in which a trench groove is formed in a first conductivity type semiconductor layer, and a second conductivity type semiconductor layer is epitaxially grown so as to bury the trench groove. The second conductivity type semiconductor layer is then removed until a surface of the first conductivity type semiconductor layer is exposed. The first conductivity type semiconductor layer is epitaxially grown on the first conductivity type semiconductor layer and the second conductivity type semiconductor layer such that the thickness of the first conductivity type semiconductor layer increases by a length which is substantially the same as a depth of the trench groove. The first conductivity type semiconductor layer is selectively removed such that the second conductivity type semiconductor layer is exposed, and the epitaxially growing of the second conductivity type semiconductor layer is repeated through selectively removing the first conductivity type semiconductor layer.

Power semiconductor switching element

Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.

Smart Power Devices and ICs Using GaAs and Wide and Extreme Bandgap Semiconductors

Abstract: We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, and diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences.

General-Purpose Clocked Gate Driver IC With Programmable 63-Level Drivability to Optimize Overshoot and Energy Loss in Switching by a Simulated Annealing Algorithm

Abstract: A general-purpose clocked gate driver integrated circuit (IC) to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with a 0.18 μm Bipolar-CMOS-DMOS process has 63 P-type MOS (PMOS) and 63 N-type MOS (NMOS) driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 40 ns time step control. In the 500 V switching measurements with a manual gate waveform optimization, the proposed gate driver reduces the IC overshoot by 25% and 41%, and the energy loss by 38% and 55% for Si-insulated-gate bipolar transistor and SiC-MOSFET, respectively, which demonstrate the feasibility of driving various power devices with the same driver. An automatic optimization by simulated annealing algorithm is introduced to fully utilize the benefit of the gate driver, and the further reduction of IC overshoot by 26% and the energy loss by 18% are achieved over the manual optimization.

I and i

Abstract: There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality. Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

Semiconductor device, and manufacturing method thereof

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

The 2018 GaN power electronics roadmap

Abstract: Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here.

Power semiconductor devices and methods of manufacture

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.