Ishiang Shih

Bio: Ishiang Shih is an academic researcher from McGill University. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 4, co-authored 9 publications receiving 95 citations.

An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range

Abstract: An operational-transconductance-amplifier (OTA) design for ultra-low voltage ultra-low power applications is proposed. The input stage of the proposed OTA utilizes a bulk-driven pseudo-differential pair to allow minimum supply voltage while achieving a rail-to-rail input range. All the transistors in the proposed OTA operate in the subthreshold region. Using a novel self-biasing technique to bias the OTA obviates the need for extra biasing circuitry and enhances the performance of the OTA. The proposed technique ensures the OTA robustness to process variations and increases design feasibility under ultra-low-voltage conditions. Moreover, the proposed biasing technique significantly improves the common-mode and power-supply rejection of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping-factor control circuit is exploited. The OTA is fabricated in a 65 nm CMOS technology. Measurement results show that the OTA provides a low-frequency gain of 46 dB and rail-to-rail input common-mode range with a supply voltage as low as 0.5 V. The dc gain of the OTA is greater than 42 dB for supply voltage as low as 0.35 V. The power dissipation is 182 $\mu{\rm W}$ at $V_{DD}=0.5\ {\rm V}$ and 17 $\mu{\rm W}$ at $V_{DD}=0.35\ {\rm V}$ .

Track and hold for Giga-sample ADC applications using CMOS technology

Abstract: This paper presents a CMOS track and hold amplifier (THA) designed and fabricated in a 130 nm CMOS technology. It is intended for analog-to-digital converters (ADCs) used in radio receivers that sample in the Giga-Hertz region. At these data rates, it is extremely difficult for data converters to reach the desired performance levels using a single data path. Rather, ADCs operating in parallel at lower clock rates are becoming the norm. Such architectures require high-performance THAs capable of capturing the signal information at the desired sampling speed. Experimentally, this work will demonstrate a 2.5 GS/s THA capable of offering an SNR of almost 46 dB, SNDR of 42.4 dB and an ENOB of almost 7 bits.

A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS

Abstract: An operational-transconductance-amplifier (OTA) design for low-voltage low-power applications is proposed. The proposed OTA incorporates bulk-driven MOS transistors in the pseudo differential pair of the input stage to concurrently enable low voltage operation and rail-to-rail input range. Using a common-mode feedforward (CMFF) circuit in the first stage to bias the following stages of the OTA obviates the need for extra biasing circuitry and improves the performance of the OTA. To further enhance the bandwidth and allow the use of smaller compensation capacitors, a compensation network based on a damping factor control circuit is exploited. To verify the theoretical findings, the OTA was fabricated in a 65 nm CMOS technology. Measurements show that the OTA provides a low-frequency gain of 46 dB at Vdd = 0.5 V, and a gain of 43 dB at Vdd = 0.35 V. The power dissipation is 182 μW at Vdd = 0.5 V, and 17 μW at Vdd = 0.35 V.

Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs

Abstract: This paper presents an analytical and comparative study on the design of the loop filter in frequency synthesizer Phase Locked Loops (PLLs). Loop filter design involves the selection of topology, type, order, poles ratio, noise contribution, and loop stability. The trade-offs involved in the design are elucidated and analyzed. The detailed analysis and simulation in this paper facilitate the selection of the loop filter that results in the optimum performance. Components selection through mathematical derivation and filter design tables is demonstrated.

A 0.6V-supply bandgap reference in 65 nm CMOS

Abstract: A bandgap voltage reference that operates from a power supply of 0.6 V is presented in this paper. The circuit is based on an all-CMOS implementation that allows operation below the base-emitter voltage limit by eliminating parasitic vertical bipolar-junction-transistors. Low-voltage design techniques are deployed to design an op-amp that can obviate the need for a start-up circuit. The design was implemented in 65 nm CMOS technology. The measured reference voltage is 275 mV with an average temperature coefficient of 176 ppm/°C from −50°C to 80°C without trimming. The circuit consumes 62 μW of power and occupies 0.011 mm2 of chip area.

Design Of Analog Cmos Integrated Circuits

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A 3-10-Ghz low-noise amplifier with wideband LC-ladder matching network

Abstract: Reactive matching is extended to wide bandwidths using the impedance property of LC-ladder filters. In this paper, we present a systematic method to design wideband low-noise amplifiers. An SiGe amplifier with on-chip matching network spanning 3-10 GHz delivers 21-dB peak gain, 2.5-dB noise figure, and -1-dBm input IP3 at 5 GHz, with a 10-mA bias current.

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Abstract: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier

Abstract: A simple high-performance architecture for bulk-driven operational transconductance amplifiers (OTAs) is presented. The solution, suitable for operation under sub 1-V single supply, is made up of three gain stages and, as an additional feature, provides inherent class-AB behavior with accurate and robust standby current control. The OTA is fabricated in a 180-nm standard CMOS technology, occupies an area of $19.8\cdot 10^{-3}\ \text{mm}^{2}$ and is powered from 0.7 V with a standby current consumption of around 36 $\mu\text{A}$ . DC gain and unity gain frequency are 57 dB and 3 MHz, respectively, under a capacitive load of 20 pF. Overall good large-signal and small-signal performances are achieved, making the solution extremely competitive in comparison to the state of the art.