Ishita Jain

Bio: Ishita Jain is an academic researcher from Indian Institute of Technology Delhi. The author has contributed to research in topics: Equivalent series resistance & Silicon on insulator. The author has an hindex of 3, co-authored 5 publications receiving 38 citations.

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Abstract: Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current. In this paper, we show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. It is found that upscaling the diameter of lower nanowires with respect to the upper nanowires improved uniformity of the current in each nanowire, but with the drawback of threshold voltage reduction. We propose to increase source/drain trench silicide depth as a more promising solution to this problem over the nanowire diameter scaling, without compromising on power or performance of these devices.

Comparison of heat outflow in dense sub-14nm contemporary NFETs: Bulk/SOI, inserted-oxide FinFET and nanowire FET

Abstract: Since the invention of iFinFET devices, there has been literature suggesting various electrical and thermal improvements it could have over gate-all-around NWFETs. In this work, we have compared contemporary NFETs for 7-nm CMOS technology node for their electrical only and thermal only performance using calibrated 3-D TCAD simulations. This allowed us to simulate relatively larger device structures required for analysis of thermal behavior of these devices with ease, while we could utilize most advanced mobility models to simulate smaller device structures to address electrical performance of these devices. While electrical performance of all these devices is comparable, SOI FinFETs show at least 30 degree Kelvin higher temperature as compared to other devices in thermal simulations, while the bulk FinFETs can achieve 40 degree Kelvin lower temperature in presence of an identical thermal power source. The nanowire and iFinFET depict moderate thermal behavior in this comparison.

Nanowire FET design for 7-nm SOI-CMOS technology

Abstract: In this paper we present analysis on a nanowire FET specific device design issue arising from the combination of stacked nanowire configuration and use of trench silicidation in the current CMOS process. Our calibrated TCAD simulation results show for the first time that nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. For nanowires with square cross-section and 6.5nm side of the square, series resistance is shown to increase by 32% between the top and bottom most nanowire. This increase in series resistance is further shown to cause 24% decrease in linear drain current.

An investigation of reliability and variability issues in nanoscale SOI and multi-gate MOSFETs: modelling, simulation and characterization

Abstract: This work encapsulates research being carried out in the Device and Wafer Level Characterization Lab at the Department of Electrical Engineering, IIT Delhi in the field of nano-electronics device characterization and modeling. Performance of different multi-gate device architectures, as well as their reliability and variability in different working conditions is investigated using measurement and simulations. The reliability of 180-nm fully and partially-depleted SOI MOSFETs has been extensively studied against heavy-ion irradiation for outer space applications. Exposure to heavy ion radiation can result in single event effects in semiconductor-based devices and circuits. Therefore, the transient response to heavy ion irradiation is presented for 6T-SRAM cell. Moreover, self-heating (SH) is an undesirable phenomenon in highly scaled sub-10 nm devices and it is also a major reliability concern. The heat accumulation in devices due to SH is explored and a comparison among nanowire FET, FinFET, and iFinFET is presented. Our results show that the device performance will be affected for space as well as analog and digital applications due to self-heating and heavy-ion irradiations. Process variability is also an obstacle at sub-10 nm device design and its proper consideration is important for analog as well as digital circuit designs. Therefore, we have extracted a SPICE based compact model for nanowire FETs from the measured data. We then run Monte-Carlo simulations to incorporate the effects of process variations on the performance of nanowire-MOSFETs.

3-D LER and RDF Matching Performance of Nanowire FETs in Inversion, Accumulation, and Junctionless Modes

Abstract: Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

Planar Growth, Integration, and Applications of Semiconducting Nanowires.

Abstract: Silicon and other inorganic semiconductor nanowires (NWs) have been extensively investigated in the last two decades for constructing high-performance nanoelectronics, sensors, and optoelectronics. For many of these applications, these tiny building blocks have to be integrated into the existing planar electronic platform, where precise location, orientation, and layout controls are indispensable. In the advent of More-than-Moore's era, there are also emerging demands for a programmable growth engineering of the geometry, composition, and line-shape of NWs on planar or out-of-plane 3D sidewall surfaces. Here, the critical technologies established for synthesis, transferring, and assembly of NWs upon planar surface are examined; then, the recent progress of in-plane growth of horizontal NWs directly upon crystalline or patterned substrates, constrained by using nanochannels, an epitaxial interface, or amorphous thin film precursors is discussed. Finally, the unique capabilities of planar growth of NWs in achieving precise guided growth control, programmable geometry, composition, and line-shape engineering are reviewed, followed by their latest device applications in building high-performance field-effect transistors, photodetectors, stretchable electronics, and 3D stacked-channel integration.

Modeling of Effective Thermal Resistance in Sub-14-nm Stacked Nanowire and FinFETs

Abstract: In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

Series Resistance Reduction in Stacked Nanowire FETs for 7-nm CMOS Technology

Abstract: Vertically stacked nanowire field effect transistors currently dominate the race to become mainstream devices for 7-nm CMOS technology node. However, these devices are likely to suffer from the issue of nanowire stack position dependent drain current. In this paper, we show that the nanowire located at the bottom of the stack is farthest away from the source/drain silicide contacts and suffers from higher series resistance as compared to the nanowires that are higher up in the stack. It is found that upscaling the diameter of lower nanowires with respect to the upper nanowires improved uniformity of the current in each nanowire, but with the drawback of threshold voltage reduction. We propose to increase source/drain trench silicide depth as a more promising solution to this problem over the nanowire diameter scaling, without compromising on power or performance of these devices.