J. Altet

Bio: J. Altet is an academic researcher. The author has contributed to research in topics: Differential amplifier & Electronic circuit. The author has an hindex of 1, co-authored 1 publications receiving 28 citations.

Differential Temperature Sensors Fully Compatible With a 0.35- $\mu$ m CMOS Process

Abstract: Four differential temperature sensors, two passive and two active, designed and fabricated in a 0.35-m standard CMOS technology, are presented and characterized. Passive sensors are based on integrated thermopiles. Each one consists of eight thermocouples (16 strips) serially connected: poly1-poly2 for the first thermopile and poly1-P+diffusion for the second one. The active sensors are based on differential amplifiers, one with single-ended output and the other with differential output. Lateral parasitic bipolar transistors are used as temperature transducer devices. Both simulated and experimental characterizations are presented. The high sensitivity of active differential temperature sensors proves the feasibility of such sensors to observe the power dissipated by devices and circuits embedded in the same silicon die, with applications to the test and characterization of circuits, packaging characterization and compensation of thermal gradients, among others.

Single-Metal Nanoscale Thermocouples

Abstract: We study the generation of thermoelectricity by nanoscale thermocouples (TCs) formed from a single layer of metal with cross-sectional discontinuity. Typically, a TC is formed when a second conductor is inserted between two sections of a first conductor forming two junctions situated at different temperatures. Here, we investigate the behavior of TCs formed not of two conductors but rather nanowires of the same metal of two cross-sectional areas. Monometallic TCs were constructed from a lithographically defined nanowire having one abrupt variation in width along its length, and tested at room temperature; these structures exploit a change in Seebeck coefficient that is present at these size scales. To investigate the thermoelectric properties of such “shape-engineered” TCs, nanoscale heaters were employed to set the local temperatures. Temperature profiles at the hot and cold junctions of the TCs were determined both by simulations and experiments. Results demonstrate that the magnitude of the open-circuit voltage, and hence the relative Seebeck coefficient, is a function of the parameters of the variations in the segment widths. The fabrication complexity of such shape-engineered monometallic nanowire TCs is greatly reduced compared to that of conventional bimetallic TCs, and could be mass-produced using simpler manufacturing techniques.

Electrothermal Design Procedure to Observe RF Circuit Power and Linearity Characteristics With a Homodyne Differential Temperature Sensor

Abstract: The focus in this paper is on the extraction of RF circuit performance characteristics from the dc output of an on-chip temperature sensor. Any RF input signal can be applied to excite the circuit under examination because only dissipated power levels are measured, which makes this approach attractive for online thermal monitoring and built-in test scenarios. A fully differential sensor topology is introduced that has been specifically designed for the proposed method by constructing it with a wide dynamic range, programmable sensitivity to dc, and RF power dissipation, as well as compatibility with CMOS technology. This paper also presents an outline of a procedure to model the local electrothermal coupling between heat sources and the sensor, which is used to define the temperature sensor's specifications as well as to predict the thermal signature of the circuit under test. A prototype chip with an RF amplifier and temperature sensor was fabricated in a conventional 0.18-μm CMOS technology. The proposed concepts were validated by correlating RF measurements at 1 GHz with the measured dc voltage output of the on-chip sensor and the simulation results, demonstrating that the RF power dissipation can be monitored and the 1-dB compression point can be estimated with less than 1-dB error. The sensor circuitry occupies a die area of 0.012 mm2, which can be shared when several on-chip locations are observed by placement of multiple temperature-sensing parasitic bipolar devices.

Strategies for built-in characterization testing and performance monitoring of analog RF circuits with temperature measurements

Abstract: This paper presents two approaches to characterize RF circuits with built-in differential temperature measurements, namely the homodyne and heterodyne methods. Both non-invasive methods are analyzed theoretically and discussed with regard to the respective trade-offs associated with practical off-chip methodologies as well as on-chip measurement scenarios. Strategies are defined to extract the center frequency and 1 dB compression point of a narrow-band LNA operating around 1 GHz. The proposed techniques are experimentally demonstrated using a compact and efficient on-chip temperature sensor for built-in test purposes that has a power consumption of 15 μW and a layout area of 0.005 mm 2 in a 0.25 μm CMOS technology. Validating results from off-chip interferometer-based temperature measurements and conventional electrical characterization results are compared with the on-chip measurements, showing the capability of the techniques to estimate the center frequency and 1 dB compression point of the LNA with errors of approximately 6% and 0.5 dB, respectively.

Thermal analysis of integrated circuit chips using a thermographic imaging technique

Abstract: This paper presents the analysis of the thermal gradients on the substrate of an integrated-circuit chip (telephone line interface chip) using thermographic imaging techniques. After taking the chip thermal image using a thermal camera and doing temperature calibration, an isothermal contour map of the chip region is drawn by digital image-processing techniques proposed in this paper. By overlaying the layout mask on the isothermal contour map of the chip region, each region of the chip is easily identified. This information is of great assistance to the designer while laying out the components on the chip. >

Nanowire Thermocouple Characterization Platform

Abstract: Thermocouples fabricated out of nanowires possess a high spatial and temporal resolution. Due to their small size, nanowires exhibit different physical properties from their bulk counterparts. One of these properties, the Seebeck coefficient, specifies how well the thermocouple converts a temperature gradient into an open-circuit voltage. We have developed a characterization platform, with which the Seebeck coefficient of nanowires can be measured as required for the calibration of nanowire thermocouples and optimization of their fabrication process.