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J. B. Lasky

Bio: J. B. Lasky is an academic researcher. The author has contributed to research in topics: Etching (microfabrication) & Wafer. The author has an hindex of 1, co-authored 1 publications receiving 603 citations.

Papers
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TL;DR: In this paper, a silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs, and the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation.
Abstract: A silicon wafer bonding process is described in which only thermally grown oxide is present between wafer pairs. Bonding occurs after insertion into an oxidizing ambient. It is proposed the wafers are drawn into intimate contact as a result of the gaseous oxygen between them being consumed by oxidation, thus producing a partial vacuum. The proposed bonding mechanism is polymerization of silanol bonds between wafer pairs. Silicon on insulator (SOI) is produced by etching away all but a few microns of one of the bonded pair. Capacitor measurements show a 27 μs minority‐carrier lifetime and no degradation of the SOI‐insulator interface. In addition, there is negligible charge at the bonding interface making the technique attractive for three‐dimensional as well as planar SOI applications.

613 citations


Cited by
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Fu Liu1, N. Awanis Hashim1, Yutie Liu1, M.R. Moghareh Abed1, Kang Li1 
TL;DR: A comprehensive overview of recent progress on the production and modification of polyvinylidene fluoride (PVDF) membranes for liquid-liquid or liquid-solid separation can be found in this article.

1,776 citations

Journal ArticleDOI
TL;DR: In this paper, the surface energy of a silicon-on-insulator was evaluated based on crack propagation theory, and it was found that the bond strength increased with the bonding temperature from about 60-85 erg/cm2 at room temperature to ≂2200 erg/ cm2 at 1400°C.
Abstract: Several aspects of a new silicon‐on‐insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face‐to‐face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10‐s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal‐oxide‐semiconductor (MOS) capacitors. The results were consistent with a negative charge de...

819 citations

Journal ArticleDOI
03 Apr 2009
TL;DR: This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of Piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.
Abstract: Piezoresistive sensors are among the earliest micromachined silicon devices. The need for smaller, less expensive, higher performance sensors helped drive early micromachining technology, a precursor to microsystems or microelectromechanical systems (MEMS). The effect of stress on doped silicon and germanium has been known since the work of Smith at Bell Laboratories in 1954. Since then, researchers have extensively reported on microscale, piezoresistive strain gauges, pressure sensors, accelerometers, and cantilever force/displacement sensors, including many commercially successful devices. In this paper, we review the history of piezoresistance, its physics and related fabrication techniques. We also discuss electrical noise in piezoresistors, device examples and design considerations, and alternative materials. This paper provides a comprehensive overview of integrated piezoresistor technology with an introduction to the physics of piezoresistivity, process and material selection and design guidance useful to researchers and device engineers.

789 citations

Journal ArticleDOI
TL;DR: In this article, the authors discuss methods of forming silicon-on-insulator (SOI) wafers, their physical properties, and the latest improvements in controlling the structure parameters.
Abstract: Silicon-on-insulator (SOI) wafers are precisely engineered multilayer semiconductor/dielectric structures that provide new functionality for advanced Si devices. After more than three decades of materials research and device studies, SOI wafers have entered into the mainstream of semiconductor electronics. SOI technology offers significant advantages in design, fabrication, and performance of many semiconductor circuits. It also improves prospects for extending Si devices into the nanometer region (<10 nm channel length). In this article, we discuss methods of forming SOI wafers, their physical properties, and the latest improvements in controlling the structure parameters. We also describe devices that take advantage of SOI, and consider their electrical characteristics.

772 citations