For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal-oxide-semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III-V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

Nanometre-scale electronics with III–V compound semiconductors

The past decade has seen rapid progress in research into high-performance Ge-on-Si photodetectors. Owing to their excellent optoelectronic properties, which include high responsivity from visible to near-infrared wavelengths, high bandwidths and compatibility with silicon complementary metal–oxide–semiconductor circuits, these devices can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and infrared imaging at low cost and low power consumption. This Review summarizes the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors. Owing to their excellent optoelectronic properties, Ge-on-Si photodetector can be monolithically integrated with silicon-based read-out circuits for applications such as high-performance photonic data links and low-cost infrared imaging at low power consumption. This Review covers the major developments in Ge-on-Si photodetectors, including epitaxial growth and strain engineering, free-space and waveguide-integrated devices, as well as recent progress in Ge-on-Si avalanche photodetectors.

High-performance Ge-on-Si photodetectors

Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.

Academic and industry research progress in germanium nanodevices

Part I. Silicon Photonics - Introduction: 1. Fabless Silicon Photonics: 1.1 Introduction 1.2 Silicon photonics - the next fabless semiconductor industry 1.3 Applications 1.4 Technical challenges and the state of the art 1.5 Opportunities 2. Modelling and Design Approaches: 2.1 Optical Waveguide Mode Solver 2.2 Wave Propagation 2.3 Optoelectronic models 2.4 Microwave Modelling 2.5 Thermal Modelling 2.6 Photonic Circuit Modelling 2.7 Physical Layout 2.8 Software Tools Integration Part II. Silicon Photonics - Passive Components: 3. Optical Materials and Waveguides: 3.1 Silicon-on-Insulator 3.2 Waveguides 3.3 Bent waveguides 3.4 Code Listings 3.5 Problems 4. Fundamental Building Blocks: 4.1 Directional couplers 4.2 Y-Branch 4.3 Mach-Zehnder Interferometer 4.4 Ring resonators 4.5 Waveguide Bragg Grating Filters 4.6 Code Listings 4.7 Problems 5. Optical I/O: 5.1 The challenge of optical coupling to silicon photonic chips 5.2 Grating Coupler 5.3 Edge Coupler 5.4 Polarization 5.5 Code Listings 5.6 Problems Part III. Silicon Photonics - Active Components: 6. Modulators: 6.1 Plasma Dispersion E 6.2 PN Junction Phase Shifter 6.3 Micro-ring Modulators 6.4 Forward-biased PIN Junction 6.5 Active Tuning 6.6 Thermo-Optic Switch 6.7 Code Listings 6.8 Problems 7. Detectors: 7.1 Performance Parameters 7.2 Fabrication 7.3 Types of detectors 7.4 Design Considerations 7.5 Detector modelling 7.5.2 Electronic Simulations 7.6 Code Listings 7.7 Problems 8. Lasers: 8.1 External Lasers 8.2 Laser Modelling 8.3 Co-Packaging 8.4 Hybrid Silicon Lasers 8.5 Monolithic Lasers 8.6 Alternative Light Sources 8.7 Problems Part IV. Silicon Photonics - System Design: 9. Photonic Circuit Modelling: 9.1 Need for photonic circuit modelling 9.2 Components for System Design 9.3 Compact Models 9.4 Directional Coupler - Compact Model 9.5 Ring Modulator - Circuit Model 9.6 Grating Coupler - S Parameters 9.7 Code Listings 10. Tools and Techniques: 10.1 Process Design Kit (PDK) 10.2 Mask Layout 11. Fabrication: 11.1 Fabrication Non-Uniformity 11.2 Problems 12. Testing and Packaging: 12.1 Electrical and Optical Interfacing 12.2 Automated Optical Probe Stations 12.3 Design for Test 13. Silicon Photonic System Example: 13.1 Wavelength Division Multiplexed Transmitter.

Silicon Photonics Design: From Devices to Systems

Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Lattice-Mismatched Semiconductor Structures with Reduced Dislocation Defect Densities and Related Methods for Device Fabrication

Defect-free germanium has been demonstrated in SiO2 trenches on silicon via Aspect Ratio Trapping, whereby defects arising from lattice mismatch are trapped by laterally confining sidewalls. Results were achieved through a combination of conventional photolithography, reactive ion etching of SiO2, and selective growth of Ge as thin as 450nm. Full trapping of dislocations originating at the Ge∕Si interface has been demonstrated for trenches up to 400nm wide without the additional formation of defects at the sidewalls. This approach shows great promise for the integration of Ge and/or III-V materials, sufficiently large for key device applications, onto silicon substrates.

Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping

Metal-organic chemical vapor deposition growth of GaAs on Si was studied using the selective aspect ratio trapping method. Vertical propagation of threading dislocations generated at the GaAs∕Si interface was suppressed within an initial thin GaAs layer inside SiO2 trenches with aspect ratio >1, leading to defect-free GaAs regions up to 300nm in width. Cross-sectional and plan-view transmission electron microscopies were used to characterize the defect reduction. Material quality was confirmed by room temperature photoluminescence measurements. This approach shows great promise for the fabrication of optoelectronic integrated circuits on Si substrates.

Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping

Recent research has demonstrated the effectiveness of the “aspect ratio trapping” technique for eliminating threading dislocations in Ge grown selectively in submicron trenches on Si substrates. In this letter, analysis of the mechanisms by which dislocation elimination is achieved has been carried out. Detailed transmission electron microscopy studies reveal that facets, when formed early in the growth process, play a dominant role in determining the configurations of threading dislocations in the films. These dislocations are shown to behave as “growth dislocations,” which are replicated during growth approximately along the facet normal and so are deflected out from the center of the selective epitaxial regions.

Study of the defect elimination mechanisms in aspect ratio trapping Ge growth

High quality GaAs epilayers grown by metal-organic chemical vapor deposition are demonstrated on a SiO2-patterned silicon substrate using aspect ratio trapping technique, whereby threading dislocations from lattice mismatch are largely reduced via trapping in SiO2 trenches during growth. A depletion-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is demonstrated on a n-doped GaAs channel with atomic-layer deposited Al2O3 as the gate oxide. The 10 μm gate length transistor has a maximum drain current of 88 mA/mm and a transconductance of 19 mS/mm. The surface mobility estimated from the accumulation drain current has a peak value of ∼500 cm2/Vs, which is comparable with those from previously reported depletion-mode GaAs MOSFETs epitaxially grown on semi-insulating GaAs substrates.

/pdf/atomic-layer-deposited-al2o3-gaas-metal-oxide-semiconductor-5i174esmn2.pdf

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

GaAs/InGaAs quantum-well lasers have been demonstrated by metallorganic chemical vapor deposition on virtual Ge substrates on Si via aspect-ratio trapping (ART) and epitaxial lateral overgrowth (ELO) Laser-structure growth is achieved in two steps: The first step is growing uncoalesced defect-free Ge stripes on a SiO 2 trench-patterned silicon substrate via ART, whereby the misfit defects originating from the Ge/Si interface are trapped by laterally confining sidewalls Defects arising from above the SiO 2 film are reduced by using an optimized ELO process followed by chemical mechanical polishing to provide a planar Ge surface The second step is overgrowing a GaAs/InGaAs laser structure on the virtual Ge substrate A number of GaAs/Ge integration issues, including Ge autodoping and antiphase domain defects in GaAs, have been overcome Despite unoptimized laser structures with high series resistance and large threshold current densities, pulsed room-temperature lasing at a wavelength of 980 nm has been demonstrated using a combination of ART and ELO This technique is very promising for the achievement of reliable GaAs-based optoelectronic devices on Si

J. Bai

Papers

Defect reduction of selective Ge epitaxy in trenches on Si(001) substrates using aspect ratio trapping

Defect reduction of GaAs epitaxy on Si (001) using selective aspect ratio trapping

Study of the defect elimination mechanisms in aspect ratio trapping Ge growth

Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique

Monolithic Integration of GaAs/InGaAs Lasers on Virtual Ge Substrates via Aspect-Ratio Trapping