scispace - formally typeset
Search or ask a question
Author

J.C. Gealow

Bio: J.C. Gealow is an academic researcher. The author has contributed to research in topics: Image processing & Digital image processing. The author has an hindex of 3, co-authored 3 publications receiving 20 citations.

Papers
More filters
Proceedings ArticleDOI
04 Jan 1998
TL;DR: This paper shows how the same technique may be applied to create a dense integrated processing element array to build pixel-parallel image processing hardware for microcomputer systems.
Abstract: Typical low-level image processing tasks require thousands of operations per pixel for each input image. The structure of the tasks suggests employing an array of processing elements, one per pixel, sharing instructions issued by a single controller. To build pixel-parallel image processing hardware for microcomputer systems, large processing element arrays must be produced at low cost. Integrated circuit designers have had tremendous success creating dense and inexpensive semiconductor memories. They handcraft circuits to perform essential functions using very little silicon area, then replicate the circuits to form large memory arrays. This paper shows how the same technique may be applied to create a dense integrated processing element array.

12 citations

Proceedings ArticleDOI
09 Nov 1997
TL;DR: A real-time image processing system for use in intelligent transportation systems that incorporates high-density pixel parallel (HDPP) processor chips into a programmable framework by utilizing the system in a time-sharing fashion.
Abstract: This paper presents a real-time image processing system for use in intelligent transportation systems. The system, run from a desktop computer, incorporates high-density pixel parallel (HDPP) processor chips into a programmable framework. By utilizing the system in a time-sharing fashion, multiple low-level image processing tasks can be implemented on the HDPP hardware. Examples of applications that have been implemented on the system and executed in real time include optical flow, template matching, and stereo vision.

5 citations


Cited by
More filters
Journal ArticleDOI
TL;DR: A bibliography of nearly 1700 references related to computer vision and image analysis, arranged by subject matter is presented, including computational techniques; feature detection and segmentation; image and scene analysis; two-dimensional shape; pattern; color and texture; matching and stereo.

94 citations

Journal ArticleDOI
TL;DR: An architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane with very low-power consumption at high-computation rates is presented.
Abstract: This paper presents an architectural overview of a pseudogeneral image processor (GIP) chip for realizing steerable spatial and temporal filters at the focal-plane. The convolution of the image with programmable kernels is realized with area-efficient and real-time circuits. The chip's architecture allows photoreceptor cells to be small and densely packed by performing all analog computations on the read-out, away from the array. The size, configuration, and coefficients of the kernels can be varied on the fly. In addition to the raw intensity image, the chip outputs four processed images in parallel. The convolution is implemented with a digitally programmable analog processor, resulting in very low-power consumption at high-computation rates. A 16/spl times/16 pixels prototype of the GIP has been fabricated in a standard 1.2-/spl mu/m CMOS process and its spatiotemporal capabilities have been successfully tested. The chip exhibits 1 GOPS/mW at 20 kft/s while computing four spatiotemporal convolutions in parallel.

78 citations

Journal ArticleDOI
TL;DR: An 80/spl times/78 pixels vision chip for focal-plane image processing is presented, which employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel.
Abstract: An 80/spl times/78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11/spl times/11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm/sup 2/ in a 1.2-/spl mu/m CMOS process. The application of the chip to line-segment orientation detection is also presented.

76 citations

Reference BookDOI
27 Jan 2000
TL;DR: Focusing on highway and railway systems, the authors stress the need for computer modeling and simulation to help design and validate complex, large-scale systems and the design of new performance metrics to estimate the performance of these systems.
Abstract: To serve the needs of the future, transportation systems must undergo a radical transformation, from the centralized paradigm to the asynchronous, distributed paradigm that integrates fast computers and high-performance networks through novel computer algorithms. Intelligent Transportation Systems takes the first step towards meeting that challenge. Focusing on highway and railway systems, the authors stress the need for computer modeling and simulation to help design and validate complex, large-scale systems and the design of new performance metrics to estimate the performance of these systems. They present the basic principles related to travel-related decision making, including coordination, control, and routing.

55 citations

Proceedings ArticleDOI
23 May 2004
TL;DR: A new imaging architecture with a linear current mode active pixel sensor (APS) with a correlated double sampling (CDS) unit for fixed pattern noise (FPN) suppression is presented.
Abstract: A new imaging architecture with a linear current mode active pixel sensor (APS) is presented. Focal plane image processing in the current domain includes a correlated double sampling (CDS) unit for fixed pattern noise (FPN) suppression. The CDS unit is composed of a first generation current conveyer circuit and a class AB cascaded current memory cell. A measured FPN of 0.9% from saturation level is achieved with the CDS unit compared to 1.9% FPN from current mode images without noise suppression circuitry. A 40 by 40 imaging array was fabricated in a standard 0.5 /spl mu/m process and its functionality was successfully tested. Theoretical analysis for second order non-linear effects is also presented.

43 citations