J.-C. Niemann

TL;DR: The GigaNoC is presented, a hierarchical Network-on-Chip that is especially suitable for scalable Chip-Multiprocessor architectures and features a packet-switched wormhole routing on-chip network that provides the backbone of the authors' multiprocesser architecture.

TL;DR: This paper addresses the architectural requirements which are coupled with the transfer of well known techniques from parallel computers onto the design of SoCs and proposes an on-chip architecture which is based on active switch boxes and is able to fill the existing design gap between an efficient use of the design space and the design complexity, with reasonable resource requirements.

TL;DR: In this paper, the authors proposed an on-chip architecture based on active switch boxes, which is able to fill the existing design gap between an efficient use of the design space and the design complexity, with reasonable resource requirements.

TL;DR: This paper addresses the design automation of instruction set extensions for application-specific processors with emphasis on network processing with a holistic methodology for the extension and optimization of a processor's instruction set.

TL;DR: A design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip is presented.