J.C. Vital

Bio: J.C. Vital is an academic researcher from Instituto Superior Técnico. The author has contributed to research in topics: CMOS & Switched capacitor. The author has an hindex of 7, co-authored 16 publications receiving 186 citations.

Systematic design for optimization of high-speed self-calibrated pipelined A/D converters

Abstract: High-speed pipelined analog-digital converters have been previously considered using optimum 1-bit per stage architectures that typically can attain untrimmed resolution of up to 10 bits. Conversion resolutions higher than 10 bits can only be achieved if calibration techniques are employed. In this case, however, this paper demonstrates that multibit, rather than single-bit resolution per-stage architectures have to be considered for optimizing the resulting area and power dissipation while minimizing stringent requirements of the constituting building blocks. Such optimization is achieved through a systematic design process that takes into account physical limitations for practical integrated circuit implementation, including thermal noise and capacitor matching accuracy. The impact of the selected pipelined configuration on the self-calibration requirements as well as on the practical feasibility of the active components is analyzed. An example is presented to consolidate the relevant conclusions.

Digital-to-analog converter using switched capacitor and transverse filter

Abstract: The converter incorporates a transversal filter. The filter delays are implemented in digital form prior to conversion into analog signals (preferably using switched capacitor techniques). One form of switched capacitor converter (with or without filtering) employs a single capacitor, common to a plurality of bits, appropriate weighting of the bits being achieved by controlling the switching.

A CMOS 4-bit MDAC with self-calibrated 14-bit linearity for high-resolution pipelined A/D converters

Abstract: This paper presents an integrated 4-bit MDAC for highspeed high-resolution pipelined ADCs which employs a code-by-code analogue self-calibration technique. Measured results from the prototypes fabricated in a 1.0 /spl mu/m CMOS technology show that the proposed self-calibration technique corrects the MDAC linearity and the interstage gain to the 14-bit level, while allowing conversion rates in the MHz range.

Systematic Design for Optimisation of Pipelined Adcs

Abstract: Contents. Abbreviations. Acknowledgements. Preface. 1. Introduction. 2. General Design Considerations in Pipelined A/D Converters. 3. Analogue Cody-By-Code Self-Calibration Technique. 4. Systematic Design Methodology for Optimisation of High-Speed Self-Calibrated Pipelined ADCS. 5. Design of a 14-Bit 5 MS/S CMOS Pipelined A/D Converter. 6. Integrated Prototypes of Pipelined ADCS and Measured Results. 7. Conclusions. Appendixes.

A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification

Abstract: Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-/spl mu/m double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm/sup 2/.

Sigma-delta digital-to-analog converter with reduced noise

Abstract: A sigma-delta digital-to-analog converter (DAC) (40) receives oversampled input data representative of an analog signal. The data may be optionally interpolated to a higher rate in a interpolator (41). A noise-shaping sigma-delta modulator (42) is connected to the output of the interpolator (41). The output of the modulator (42) is provided to a finite impulse response (FIR) filter (43). The FIR filter (43) has a frequency response characteristic which reduces the shaped noise and aliased components. This noise has a tendency to intermodulate back into the DAC's passband. The FIR filter (43) uses a series of flip-flops (81, 82, 83) functioning as delay elements with well-controlled timing edges. The outputs of the flip-flops (81, 82, 83) control current sources (91, 92, 93) weighted according to corresponding filter coefficients. The outputs of the current sources (91, 92, 93) are then summed in a summing device such as an amplifier (101).

Integrated chaos generators

Abstract: This paper surveys the different design issues, from mathematical model to silicon, involved in the design of analog CMOS integrated circuits for the generation of chaotic behavior.

Method and apparatus for use in switched capacitor systems

Abstract: Systems, methods, and integrated circuits employ switch capacitor technology for digital to analog conversion. In one embodiment a DAC receives a multi-bit digital signal. The DAC has a switch capacitor network with a plurality of sub DACs. Each of the sub DACs receives an associated bit of the multi-bit digital signal. The capacitance within each of the sub DACs receives an amount of charge in response to the associate bit. At least two of the sub DACs share charge with one another, and the network outputs at least one analog signal indicative of a sum of values of each bit in the multi-bit digital signal.

D/A converter and delta-sigma D/A converter

Abstract: A D/A converter for converting a given digital signal into an analog signal includes a plurality of capacitors (C1, C2 ..., Ci) for storing an electric charge corresponding to a predetermined reference voltage (Vr + or Vr-). The reference voltage is selected depending on the digital signal during a period when a clock 1 is at a high level. A switch selection (SUG1 - SUGi, SB) is used to connect each of the plurality of capacitors between an input terminal and an output terminal of an operational amplifier 100 during a period when a clock 2 is at a high level.