Author
J. Cai
Bio: J. Cai is an academic researcher from IBM. The author has contributed to research in topics: Silicon on insulator & CMOS. The author has an hindex of 10, co-authored 22 publications receiving 472 citations.
Papers
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IBM1
TL;DR: In this article, the authors present a fully integrated 14nm CMOS technology featuring fin-FET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs.
Abstract: We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading ‘scale-out’ processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ∼0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for ‘scale-up’ enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.
137 citations
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IBM1
TL;DR: In this article, a novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths, despite the presence of high halo doping.
Abstract: A novel mobility extraction technique showed that the mobility enhancements in strained Si MOSFETs were retained in deep sub-100 nm channel lengths. Mobility measurement in devices with channel lengths down to 40 nm was demonstrated by a dR/dL extraction method. The results confirmed and quantified the mobility enhancements despite the presence of high halo doping in scaled strained Si MOSFETs.
84 citations
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IBM1
TL;DR: In this paper, the authors used the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel and demonstrated the first planar single gate nFET with 8 nm gate-length.
Abstract: The ultra-thin SOI (UTSOI) device is an attractive choice for sub-10 nm gate-length scaling. In this work the major issues for UTSOI are addressed. External resistance is minimized by using the raised extension (REX) process flow which features an offset spacer to minimize the region of UTSOI outside the channel. The REX process scheme is used to demonstrate improved pFET performance and also to demonstrate the first planar single gate nFET with 8 nm gate-length. High temperature mobility measurements show that the channel thickness can be scaled further than previously predicted. UTSOI devices with tungsten gates and HfO/sub 2/ gate dielectrics having appropriate threshold voltages are presented for the first time.
60 citations
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01 Dec 2009TL;DR: In this paper, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs was demonstrated.
Abstract: This work demonstrates, for the first time, the reduction of random telegraph noise (RTN) in high-к / metal gate (HK / MG) stacks incorporated in 22 nm generation FETs. Many thousands of such FETs have been fabricated, measured, and analyzed using a statistical technique to separate RTN as a major noise component from 1/f noise as a minor component. Based on a statistical comparison of these FETs, we find that high temperature forming gas annealing can suppress RTN threshold voltage variation (ΔV th ). In addition, properly annealed HK FETs have smaller RTN ΔV th than SiON FETs, due mostly to fewer traps and partly to thinner inversion thickness in HK / MG. Based on these results, we project that random dopant fluctuations will have a greater impact on SRAM yield than RTN until at least the 15 nm generation, for doped channel FETs.
33 citations
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IBM1
TL;DR: In this paper, the scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported, indicating strain-induced enhancement can be sustained in future technology nodes.
Abstract: The scaling behavior of current drive enhancements in strained-silicon NFETs on SiGe-on-insulator (SGOI) is reported. SGOI NFET enhancement exhibits only moderate channel length dependence down to sub-50 nm regime, indicating strain-induced enhancement can be sustained in future technology nodes. This is contrary to some previous reports which suggested dramatic reduction of strain-induced NFET current enhancement with channel length scaling. A novel analysis technique was developed to account for the difference in self-heating in SGOI and SOI devices to enable intrinsic device performance comparison. Additive effects of biaxial strain from the Si/SiGe heterostructure and process-induced uniaxial stress are experimentally demonstrated for the first time.
33 citations
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IBM1
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Abstract: Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.
2,680 citations
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TL;DR: In this paper, a comprehensive review of all the important theoretical and experimental advances on silicene to date, from the basic theory of intrinsic properties, experimental synthesis and characterization, modulation of physical properties by modifications, and finally to device explorations is presented.
676 citations
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IBM1
TL;DR: In this paper, the authors focus on approaches to continue CMOS scaling by introducing new device structures and new materials, including high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET and strained-silicon FET.
Abstract: This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.
644 citations
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TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results
558 citations
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TL;DR: This paper discusses device and material options to improve device performance when conventional scaling is power-constrained, separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior.
Abstract: To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.
433 citations