J. Castineira

Bio: J. Castineira is an academic researcher. The author has contributed to research in topics: Throughput (business) & Encryption. The author has an hindex of 1, co-authored 1 publications receiving 44 citations.

AES-128 Cipher. High Speed, Low Cost FPGA Implementation

Abstract: The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen, has been selected as the official advanced encryption standard (AES) and it is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 64-bit FPGA implementation of the 128- bit block and 128 bit-key AES cipher. Selected FPGA Family is Spartan 3. The cipher consumes 52 clock cycles for algorithm encryption, resulting in a throughput of 120 Mbps. Synthesis results in the use of 1643 slices, 975 flip flops, 3055 4-input look up tables and operates at 224 Mbps (maximum throughput). The design target was optimization of speed and cost.

High Throughput, Pipelined Implementation of AES on FPGA

Abstract: The FPGA-based high throughput 128 bits AES cipher processor is proposed in this paper. We present an equivalent pipelined AES architecture working on CTR mode to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The equivalent pipelined architecture does not change the data stream direction but change the inner process order in round transformation. Xilinx Foundation ISETM 10.1 FPGA design tool is used in the synthesis of the design. And the throughput of 73.737Gbps, clock frequency of 576.07MHz and resource efficiency of 3.21Mbps/LUT are provided by the proposed equivalent pipelined AES architecture. The proposed design reach higher throughput than the other designs up to date, and its resource efficiency is also very high.

Advanced Encryption Standard Algorithm: Issues and Implementation Aspects

Abstract: Data encryption has become a crucial need for almost all data transaction application due to the large diversity of the remote information exchange. A huge value of sensitive data is transferred daily via different channels such as e-commerce, electronic banking and even over simple email applications. Advanced Encryption Standard (AES) algorithm has become the optimum choice for various security services in numerous applications. Therefore, many researches get focused on that algorithm in order to improve its efficiency and performance. This paper presents a survey about the cutting edge research conducted for the AES algorithm issues and aspects in terms of developments, implementations and evaluations. The contribution of this paper is targeted toward building a base for future development and implementation of the AES algorithm. It also opens door for implementing the AES algorithm using some machine learning techniques.

An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box

Abstract: In this paper an efficient structural architecture is proposed for AES Encryption process to achieve high throughput with less device utilization. Breakable and controllable structures for main AES blocks at the gate level are designed and used here. The control unit using high speed combinational logic circuit is designed to control the AES structural architecture. Modified MUX based S-Box is introduced in AES instead of S-Box to reduce the area without affecting the throughput. In addition Encryption process Mix-columns transformation is modified to reduce the hardware complexity. The five stage subpipelining is introduced in AES MUX based S-Box with six pipelining stages in AES encryption process to increase throughput further. The aim of this work is to investigate both the existing and new architectures. The modified MUX based S-Box for Rijndael algorithm has been used in the 128-bit AES encryption process. The role of five stage sub-pipelined MUX based S-Box of 128-bit pipelined AES is to reduce the critical path delay to minimum for achieving high clock frequency. The rows of multiplexer in AES architecture were used for the breaking and controlling of the design. The modified 128-bit encryption was implemented on Virtex-4, Virtex-5, and Spartan 3 FPGA Devices. The results of the proposed architecture are analysed, throughput and area for the implemented design are calculated. The calculated results are compared with other architecture (Liberatori et al. in 3rd southern proceedings of the IEEE conference on programmable logic, SPL'07, pp 195---198, 2007; Farashahi et al. in Microelectron J 45:1014---1025, 2014; Good and Benaissa in IET Inf Secur 1(1):1---10, 2007; Sireesha and Madhava Rao in Int J Sci Res 3(9):1---5, 2013; Gielata et al. in Proceedings of the international conference on signals and electronic systems (ICSES), pp 137---140, 2008; El Adib and Raissouni in Int J Inf Netw Secur 1(2):1---10, 2012; Good and Benaissa in Lecture Notes Computer Science, vol 3659, pp 427---440, 2005). From the results it is obtained that the proposed architecture gives 58 % improvement with 1.08 % reduction in area.

Studies on high-speed hardware implementation of cryptographic algorithms

Abstract: Education Dec. 16, 2008 Doctor of Science in Technology, Helsinki University of Technology, Espoo, Finland. Major: signal processing technology, minor: information technology Dec. 15, 2003 Master of Science in Technology, Helsinki University of Technology, Espoo, Finland. Study programme of electronics and electrical engineering, part one with extended curriculum in science, major: signal processing for communications May 31, 1998 Matriculation, Naantalin lukio, Naantali, Finland. Senior high school degree, matriculation examination: the highest grade (laudatur) in mathematics and physics/chemistry