scispace - formally typeset
Search or ask a question
Author

J. Chen

Bio: J. Chen is an academic researcher from Université catholique de Louvain. The author has contributed to research in topics: Silicon on insulator & CMOS. The author has an hindex of 4, co-authored 8 publications receiving 382 citations.

Papers
More filters
Journal ArticleDOI
TL;DR: An original scheme is presented, which allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method.
Abstract: The maturation of low-cost silicon-on-insulator (SOI) MOSFET technology in the microwave domain has brought about a need to develop specific characterization techniques. An original scheme is presented, which, by combining careful design of probing and calibration structures, rigorous in situ calibration, and a new powerful direct extraction method, allows reliable identification of the parameters of the non-quasi-static (NQS) small-signal model for MOSFETs. The extracted model is shown to be valid up to 40 GHz.

138 citations

Journal ArticleDOI
TL;DR: In this article, N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for lowvoltage, low-power microwave applications.
Abstract: TiSi2, CoSi2, and NiSi self-aligned silicide processes have been studied, compared, and applied to thin-film silicon-on-insulator technology. Compared to TiSi2, CoSi2 and NiSi have the advantages of wider process temperature window, no significant doping retarded reaction, narrow runner degradation, and thin-film degradation. Therefore, they are more suitable for thin-film silicon-on-insulator technology. N-type field effect transistors have been fabricated in a complementary metal oxide-semiconductor compatible thin-film silicon-on-insulator technology with titanium, cobalt, and nickel self-aligned silicide processes for low-voltage, low-power microwave applications. The initial thicknesses of titanium, cobalt, and nickel are 30, 13, and 25 nm, respectively. The gate sheet resistances are 6.2, 4.4, and 2.9 Omega/square, respectively, and the total source/drain series resistances are 700, 290, and 550 Omega mu m, respectively. High-frequency measurement results are also presented.

104 citations

Journal ArticleDOI
TL;DR: In this article, the authors demonstrate that FD SOI MOSFETs exhibit near-ideal body factor, sub-threshold slope and current drive properties for mixed fabrication and operation under low supply voltage of analog, digital and microwave components.
Abstract: This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the field of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets are both theoretically and experimentally investigated. Original circuit studies then show how a basic FD SOI CMOS process allows for the mixed fabrication and operation under low supply voltage of analog, digital and microwave components with properties significantly superior to those obtained on bulk CMOS. Experimental circuit realizations support the analysis.

83 citations

Proceedings ArticleDOI
30 Sep 1996
TL;DR: In this paper, the high-frequency performances of microwave transistors fabricated using a standard fully-depleted SOI CMOS process are described, which are compatible with analog and digital circuits fabricated using the same low-cost process.
Abstract: Summary form only given. Recently, it has been demonstrated that the use of high-resistivity SOI (SIMOX) substrates (5,000 and 10,000 /spl Omega/.cm) yields MOSFETs which offer interesting microwave performances. Indeed unity-gain frequencies (f/sub T/) of 14 and 23.6 GHz and maximum oscillation frequencies (f/sub max/) of 21 and 32 GHz have been reported for effective gate lengths of 0.36 and 0.25 /spl mu/m, respectively, and using supply voltages ranging from 3 to 5 volts. Such devices can be integrated with planar lines to implement MMIC circuits. These transistors were fabricated using a dedicated MOS process, called MICROX/sup TM/, which uses non-standard CMOS features, such as a metal (gold) gate and air-bridge metallisation. In this work, the high-frequency performances of microwave transistors fabricated using a standard fully-depleted SOI CMOS process are described. These devices are, therefore, compatible with analog and digital circuits fabricated using the same low-cost process.

63 citations

Journal ArticleDOI
TL;DR: Tungsten metallization technology has been developed for high temperature silicon-on-insulator devices and circuits as discussed by the authors, and experiments on tungsten evaporation, plasma etching, annealing and lift-off process for the contact pad will be described in detail.
Abstract: Tungsten metallization technology has been developed for high temperature silicon-on-insulator devices and circuits. The experiments on tungsten evaporation, plasma etching, annealing and lift-off process for the contact pad will be described in detail. Contact resistances were measured and compared with that of an aluminum metallization system. No significant degradation was observed by static measurement from room temperature up to 320 degrees C.

4 citations


Cited by
More filters
Patent
10 Oct 2002
TL;DR: In this paper, a fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements, which includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.
Abstract: An RF switch circuit and method for switching RF signals that may be fabricated using common integrated circuit materials such as silicon, particularly using insulating substrate technologies. The RF switch includes switching and shunting transistor groupings to alternatively couple RF input signals to a common RF node, each controlled by a switching control voltage (SW) or its inverse (SW_), which are approximately symmetrical about ground. The transistor groupings each comprise one or more insulating gate FET transistors connected together in a “stacked” series channel configuration, which increases the breakdown voltage across the series connected transistors and improves RF switch compression. A fully integrated RF switch is described including control logic and a negative voltage generator with the RF switch elements. In one embodiment, the fully integrated RF switch includes an oscillator, a charge pump, CMOS logic circuitry, level-shifting and voltage divider circuits, and an RF buffer circuit.

240 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m.
Abstract: This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).

210 citations

01 Jan 2000
TL;DR: The proposed de-embedding method addresses issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS and allows large devices to be measured with high accuracy.
Abstract: In this paper, a de-embedding method is proposed for conducting accurate on-wafer device measurements in the gi- gahertz range. The method addresses issues of substrate coupling and contact effects and is therefore suitable for measurements with lossy technologies such as CMOS. The method assumes a probe-tip two-port calibration performed with well-known techniques and impedance substrates. By employing a physical interpretation of the test-fixture, the method alleviates a number of known prob- lems with common de-embedding procedures. Four distinct math- ematical steps are suggested to de-embed parasitics for the test-fix- ture to give an accurate measurement of the device under test. By introducing a simple compensation factor for in-fixture stan- dard imperfections, the proposed method allows large devices to be measured with high accuracy. The applicability of the method is demonstrated with measurements up to 12 GHz.

176 citations

Patent
11 Jul 2006
TL;DR: In this article, a method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) was described, which can be adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFs, thereby yielding improvements in FET performance.
Abstract: A method and apparatus for use in improving the linearity characteristics of MOSFET devices using an accumulated charge sink (ACS) are disclosed. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one exemplary embodiment, a circuit having at least one SOI MOSFET is configured to operate in an accumulated charge regime. An accumulated charge sink, operatively coupled to the body of the SOI MOSFET, eliminates, removes or otherwise controls accumulated charge when the FET is operated in the accumulated charge regime, thereby reducing the nonlinearity of the parasitic off-state source-to-drain capacitance of the SOI MOSFET. In RF switch circuits implemented with the improved SOI MOSFET devices, harmonic and intermodulation distortion is reduced by removing or otherwise controlling the accumulated charge when the SOI MOSFET operates in an accumulated charge regime.

175 citations

Journal ArticleDOI
10 Jul 2006
TL;DR: The feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication.
Abstract: Wireless sensor nodes are autonomous devices incorporating sensing, power, computation, and communication into one system. Applications for large scale networks of these nodes are presented in the context of their impact on the hardware design. The demand for low unit cost and multiyear lifetimes, combined with progress in CMOS and MEMS processing, are driving development of SoC solutions for sensor nodes at the cubic centimeter scale with a minimum number of off-chip components. Here, the feasibility of a complete, cubic millimeter scale, single-chip sensor node is explored by examining practical limits on process integration and energetic cost of short-range RF communication. Autonomous cubic millimeter nodes appear within reach, but process complexity and substantial sacrifices in performance involved with a true single-chip solution establish a tradeoff between integration and assembly.

174 citations