Miniaturization has steadily increased the economic usefulness of digital electronics through the past two decades. A variety of physical arguments are brought to bear on the question of how far miniaturization can be extended. The implications of the laws of quantum mechanics and thermodynamics for information storage are examined. The need for power dissipation in electrical information processing is demonstrated and the limits set on miniaturization by the problems of removing the heat thereby produced are estimated. limits with origins in properties of the materials used to make electronic devices are reviewed. The potential performance of various technologies based on nonsemiconductor phenomena is estimated and compared with the limits found for planar silicon technology. Attempts are made to guess at all of the many unknown parameters that enter into broadly applicable quantitative expressions of the properties of logic circuitry so that actual values of the limits can be estimated.

Physical limits in digital electronics

It is shown that there exists an absolute lower limit to device size and an absolute upper limit to packing density of nonredundant semiconductor devices, whether integrated or nonintegrated, based on fundamental physical phenomena such as statistical variations in impurity distribution, maximum resolution of semiconductor fabrication methods, power density and influence of cosmic rays. The influence of these phenomena falls in two categories, namely failures that appear during the fabrication of the devices (impurity distribution, dividing operation) and failures that appear during use. The latter may be temporary failures (cosmic ray ionization, carrier fluctuations) or permanent failures (atomic displacements by cosmic rays, heat generation). For a medium size computer (105 components) with a reasonable life expectancy (1 month mean time between failures), the minimum device size under reasonable conditions is approximately (10?)3, which is not far from devices now in the planning stage and within reach with eidsting techniques. It is within a factor of 2-5 of the dimensions of the active region of many devices of today. As microminiaturization by mere reduction in size appears headed for a not too distant limit it appears necessary from a device point of view to consider remedies which also have been suggested from a system point of view, namely redundancy, self-organizing systems, negative feedback, etc.

Minimum Size and Maximum Packing Density of Nonredundant Semiconductor Devices

By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed.

The Effects of Interconnections on High-Speed Logic Circuits

Power dissipation in microprocessors is projected to reach a level that may necessitate chip-level liquid cooling in the near future. An on-chip microchannel heat sink can reduce the total thermal interfaces between an integrated circuit chip and the convective cooling medium and therefore yield smaller junction-to-ambient thermal resistance. This paper reports the fabrication, assembly, and testing of a silicon chip with complementary metal-oxide-semiconductor process compatible microchannel heat sink and thermofluidic chip input/output (I/O) interconnects fabricated using wafer-level batch processing. Ultra-small form factor, low-cost fabrication and assembly (system integration) are achieved for 2D and 3D chips, as the microchannel heat sink is fabricated directly on back-side of each chip. Through-wafer electrical and fluidic vias are used to interconnect the monolithically integrated microchannel heat sink to thermofluidic chip I/O interconnections. The feasibility of the novel fluidic I/O interconnect is demonstrated through preliminary thermal resistance measurements.

Integrated Microfluidic Cooling and Interconnects for 2D and 3D Chips

This paper describes a novel 3D integration technology that enables the integration of electrical, optical, and microfluidic interconnects in a 3D die stack. The electrical interconnects are used to provide power delivery and signaling, the optical interconnects are used to enable optical signal routing to all levels of the 3D stack, and the microfluidic interconnects are used to cool each level in the 3D stack and thus enable stacking of high-performance (high-power) dice. These interconnects are integrated in a 3D stack both as through-silicon vias (TSVs) and as input/output (I/O) interconnects. Design trade-offs (TSV density, power supply noise, thermal resistance, and pump size), fabrication, and assembly are reported.

3D heterogeneous integrated systems: Liquid cooling, power delivery, and implementation

http://ieeexplore.ieee.org/iel6/8304/25936/01157266.pdf

J. Early

Papers

Speed, power and component density in multielement high-speed logic systems