Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mutual interaction between the two quadrature mixers, which results in different high- and low-side conversion gains, and unexpected IIP2 and IIP3 values. With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.

Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers

A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

This paper presents a resistive feedback broadband LNA in 90 nm CMOS which occupies 50 mum times 270 mum of active area The LNA has 7 GHz 3 dB bandwidth and >24 dB voltage gain Across 05-6 GHz, its input matching is better than -10 dB, noise figure below 25 dB, and iIP3 better than -8 dBm Techniques to improve linearity in resistive feedback LNAs are discussed in detail The LNA also provides an additional low power mode operation

A 0.5-6 GHz Improved Linearity, Resistive Feedback 90-nm CMOS LNA

.......................................................................................................................... I Acknowledgement ......................................................................................................... IV TABLE OF CONTENTS ............................................................................................... V LIST OF FIGURES .................................................................................................... VIII LIST OF TABLES ........................................................................................................ XI 1. Chapter 1: Introduction ............................................................................................ 1 1.1 Motivation......................................................................................................... 1 1.2 Objective and Major contributions..................................................................... 2 1.3 Thesis organization ........................................................................................... 4 2. Chapter 2: Literature review on LNA design ............................................................ 5 2.1 Receiver architectures ....................................................................................... 5 2.1.1 Heterodyne Receiver .................................................................................. 5 2.1.2 Homodyne Receiver (Direct conversion receiver)....................................... 7 2.2 Design parameters ............................................................................................. 9 2.2.1 Sensitivity .................................................................................................. 9 2.2.2 Noise figure ............................................................................................... 9 2.2.3 Harmonic distortion and Intermodulation ................................................. 12 2.2.4 Dynamic Range ........................................................................................ 17 2.2.5 S-Parameters ............................................................................................ 18 2.3 Introduction to LNA ........................................................................................ 20 2.3.1 Performance trade-offs in LNA design ..................................................... 22 2.3.2 Input Architecture .................................................................................... 29 2.3.3 Tuning techniques of LNA's Load ............................................................ 40

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Ultra low-power low-noise amplifier designs for 2.4 GHz ISM band applications

A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on-chip balun matching network in 45nm standard digital CMOS process demonstrates saturated power of +23dBm. The average efficiency is +5% and peak efficiency is +15%. A standalone class AB CMOS power amplifier with on-chip BALUN matching network was also produced and detailed characterization data is presented. Using digital predistortion, an EVM of −28dB is achieved at 19dBm for 5GHz band and 2.5GHz band for standalone Power Amplifier.

Fully integrated 23dBm transmit chain with on-chip power amplifier and balun for 802.11a application in standard 45nm CMOS process

A prototype 1-6GHz multi-band sampled sliding-IF receiver with discrete-time channel select filtering in a 90nm low resistivity substrate, strained-Si digital CMOS process is presented. The core receiver has an inductor-less wideband LNA front-end, a sampled mixer, and a combination of programmable poly-phase FIR and IIR filter for baseband filtering. The receiver achieves a noise figure (NF) of -19dBm for bands between 1-6GHz. The receiver when used in a system with an external tuned LNA (2.5dB NF) on the front end module achieves NF of -34dBm for the WiFi bands. The die area for the entire receiver is 0.8mm2 and consumes 89mW

Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process

A multi-standard direct conversion receiver achieves 2.2 dB NF at 6 GHz with a 15 kHz flicker noise corner. 1 dB RF bandwidth is 4.9-6 GHz, power dissipation is 56 mW from 1.3 V and active die area is less than 1.2 mm2, including the input matching network. Inband P1 dB and IIP3 at maximum gain (39 dB) are -30 dBm and -18 dBm, respectively, and three gain steps of 6 dB are provided. DC offset from self mixing is less than 10 mV.

J.-H.C. Zhan

Papers

Multi-Band (1-6GHz), Sampled, Sliding-IF Receiver with Discrete-Time Filtering in 90nm Digital CMOS Process

A 2.2dB NF, 4.9–6GHz direct conversion multi-standard RF receiver front-end in 90nm CMOS