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J.H. Patel

Bio: J.H. Patel is an academic researcher. The author has contributed to research in topics: Electronic circuit & Basis path testing. The author has an hindex of 1, co-authored 1 publications receiving 19 citations.

Papers
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Proceedings ArticleDOI
30 Apr 2000
TL;DR: This paper presents a testing methodology and efficient algorithms to establish an upper bound (in most cases greater than the circuit clock period) on the circuit delay by testing only the paths in the basis path set.
Abstract: Paths in a circuit share many lines and gates and hence, under specific assumptions, path delays are linearly related to each other. The delays of all the paths in a circuit can be expressed as a linear combination of the delays of a small subset of paths called the basis path set. In this paper we present a testing methodology and efficient algorithms to establish an upper bound (in most cases greater than the circuit clock period) on the circuit delay by testing only the paths in the basis path set. Since the size of the basis path set has been shown to be at most linear in the size of the circuit, this technique has the potential of drastically reducing the number of paths that have to be tested. Experimental results for benchmark circuits are given.

19 citations


Cited by
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Journal ArticleDOI
TL;DR: A unified formal framework for integrated circuits (ICs) Trojan detection that can simultaneously employ multiple noninvasive side-channel measurement types (modalities) and a new submodular formulation of the problem objective function is devised.
Abstract: This paper presents a unified formal framework for integrated circuits (ICs) Trojan detection that can simultaneously employ multiple noninvasive side-channel measurement types (modalities). After formally defining the IC Trojan detection for each side-channel measurement and analyzing the complexity, we devise a new submodular formulation of the problem objective function. Based on the objective function properties, an efficient Trojan detection method with strong approximation and optimality guarantees is introduced. Signal processing methods for calibrating the impact of interchip and intrachip correlations are presented. We define a new sensitivity metric that formally quantifies the impact of modifications to each existing gate that is affected by Trojan. Using the new metric, we compare the Trojan detection capability of different measurement types for static (quiescent) current, dynamic (transient) current, and timing (delay) side-channel measurements. We propose four methods for combining the detection results that are gained from different measurement modalities and show how the sensitivity results can be used for a systematic combining of the detection results. Experimental evaluations on benchmark designs reveal the low-overhead and effectiveness of the new Trojan detection framework and provides a comparison of different detection combining methods.

118 citations

Proceedings ArticleDOI
10 Nov 2008
TL;DR: Experimental results on benchmark circuits show that using compressed sensing theory can characterize the post-silicon variations with a mean accurately of 95% in the pertinent sparse basis.
Abstract: We address post-silicon characterization of the unique gate delays and their timing distributions on each manufactured IC. Our proposed approach is based upon the new theory of compressed sensing. The first step in performing timing measurements is to find the sensitizable paths by traditional testing methods. Next, we show that the timing variations are sparse in the wavelet domain. The sparsity is exploited for estimation of the gate delays using the compressed sensing theory. This estimation method requires significantly less number of timing measurements compared to the case where the dependence between the gate delays is not directly integrated within the estimation framework. We discuss a number of applications for the new post-silicon timing characterization method. Experimental results on benchmark circuits show that using compressed sensing theory can characterize the post-silicon variations with a mean accurately of 95% in the pertinent sparse basis.

46 citations

Journal ArticleDOI
TL;DR: A method to locate possible segments that cause extra delays on circuit paths by guiding the solutions of the linear constraints solved by a linear programming solver to build linear constraints, which greatly increases the efficiency of the diagnosis process.
Abstract: Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we propose a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the linear constraints solved by a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. Besides, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. Three main features of the proposed method are that: 1) it does not assume any delay fault model; 2) it derives diagnosis results directly from test data; and 3) it is able to diagnose failures caused by multiple delay defects. These features make our proposed method more realistic on solving the real problems occurring in the manufacturing process. In the experimental results, for most cases of injecting 5% of the longest path delay, the probabilities are over 90% for locating faulty segments within the list of top-ten suspects, and the average rankings, that is often referred to as first hit rank (FHR), which is defined as the rank of the first hit of the defect in the ranking list, are among the top five suspect locations for single fault injection. In the experimental results of multiple faults injection, the average FHRs are also lower than 5 for all cases of injecting 1% of the longest path delay.

33 citations

Proceedings ArticleDOI
08 Nov 2005
TL;DR: A method to locate possible segments that cause extra delays on circuit paths by guiding the delay bounds of the tested paths to build linear constraints with a linear programming solver and reducing the search space by identifying indistinguishable segments.
Abstract: Diagnosis tools can be used to speed up the process for finding the root causes of functional or performance problems in a VLSI circuit. In this paper, we proposed a method to locate possible segments that cause extra delays on circuit paths. We use the delay bounds of the tested paths to build linear constraints. By guiding the solutions of the above linear constraints with a linear programming solver, we can identify segments with extra delays. Also, with the ranks of segment delays, we can prioritize the search for possible locations of failed segments. In the diagnosis framework, we also propose to reduce the search space by identifying indistinguishable segments. Essentially, we cannot separate segments in the same category no matter which segments have faults. This approach greatly increases the efficiency of the diagnosis process. In the experimental results, for most cases of injecting 10% of the longest paths delays, the probabilities are over 90% for locating faulty segments within the list of top-ten candidates, and the average rankings are among the top 5 suspect locations

31 citations

Patent
28 Mar 2002
TL;DR: In this article, a method and apparatus for generating test patterns used to test an integrated circuit (IC) is presented, which combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within a reasonable amount of time.
Abstract: A method and apparatus for generating test patterns used to test an integrated circuit (IC). The apparatus comprises first logic that determining a subset of transition fault sites on an IC to be tested, second logic that identifies a longest sensitizable path through each transition fault site of the subset of transition fault sites, and third logic that generates a bounded set of test patterns that test the identified longest sensitizable paths through each transition fault site of the subset of transition fault sites. The present invention combines various aspects of transition fault modeling and path delay fault modeling to enable global delay testing of an IC within reasonable amount of time.

24 citations