J
J. J. Sun
Researcher at Motorola
Publications - 9
Citations - 218
J. J. Sun is an academic researcher from Motorola. The author has contributed to research in topics: Magnetoresistive random-access memory & Memory cell. The author has an hindex of 6, co-authored 8 publications receiving 176 citations.
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Proceedings ArticleDOI
Demonstration of a Reliable 1 Gb Standalone Spin-Transfer Torque MRAM For Industrial Applications
Sanjeev Aggarwal,Kerry Joseph Nagel,G. Shimon,J. J. Sun,Thomas W. Andre,Syed M. Alam,Hamid Almasi,M. DeHerrera,Brian M. Hughes,Sumio Ikegawa,J. Janesky,H. K. Lee,H. Lu,Frederick B. Mancoff +13 more
TL;DR: In this article, the authors describe a fully functional 1 Gb standalone spin-transfer torque magnetoresistive random access memory (STT-MRAM) integrated on 28 nm CMOS and based on perpendicular magnetic tunnel junctions.
Proceedings ArticleDOI
CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications
Danny Pak-Chum Shum,Dimitri Houssameddine,S. T. Woo,Y. S. You,J. Wong,K. W. Wong,C. C. Wang,Kangho Lee,K. Yamane,Vinayak Bharat Naik,Chim Seng Seet,Taiebeh Tahmasebi,C. Hai,H. Yang,Naganivetha Thiyagarajah,R. Chao,J. W. Ting,N. L. Chung,T. Ling,T. H. Chan,S. Y. Siah,Rajesh R. Nair,Sarin A. Deshpande,Renu Whig,Kerry Joseph Nagel,Sanjeev Aggarwal,M. DeHerrera,J. Janesky,Ming-Wei Lin,H.-J. Chia,M. Hossain,H. Lu,Sumio Ikegawa,Frederick B. Mancoff,G. Shimon,Jon M. Slaughter,J. J. Sun,Michael Tran,Syed M. Alam,Thomas W. Andre +39 more
TL;DR: An unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array with full array functionality, process uniformity and reliability, and 10 years data retention at 125C with extended endurance to ∼ 107 cycles is presented.
Proceedings ArticleDOI
High density ST-MRAM technology (Invited)
Jon M. Slaughter,Nicholas D. Rizzo,J. Janesky,Renu Whig,Frederick B. Mancoff,Dimitri Houssameddine,J. J. Sun,Sanjeev Aggarwal,Kerry Joseph Nagel,Sarin A. Deshpande,Syed M. Alam,Thomas W. Andre,P. LoPresti +12 more
TL;DR: Key properties for commercial ST-MRAM circuits are reviewed, the challenges to achieving the many performance and scaling goals that are being addressed in current development around the world are discussed, recent results in the field are presented, and first results from a new, fully-functional 64Mb, DDR3, ST- MRAM circuit are presented.
Proceedings ArticleDOI
A 0.18 /spl mu/m 4Mb toggling MRAM
M. Durlam,D. Addie,Johan Åkerman,Brian R. Butcher,P. Brown,J. Chan,M. DeHerrera,B.N. Engel,B. Feil,Gregory W. Grynkewich,J. Janesky,M. Johnson,Kelly W. Kyler,J. Molla,J. Martin,K. Nagel,J. Ren,Nicholas D. Rizzo,T. Rodriguez,L. Savtchenko,J. Salter,Jon M. Slaughter,K. Smith,J. J. Sun,M. Lien,K. Papworth,P. Shah,W. Qin,R. Williams,L. Wise,Saied N. Tehrani +30 more
TL;DR: In this paper, a low power 4Mb magnetoresistive random access memory (MRAM) with a new magnetic switching mode is presented for the first time, which is based on a 1-Transistor 1-Magnetic Tunnel Junction (1TIMTJ) bit cell.
Proceedings ArticleDOI
Technology for reliable spin-torque MRAM products
Jon M. Slaughter,Kerry Joseph Nagel,Renu Whig,Sarin A. Deshpande,Sanjeev Aggarwal,M. DeHerrera,J. Janesky,Ming-Wei Lin,H.-J. Chia,M. Hossain,Sumio Ikegawa,Frederick B. Mancoff,G. Shimon,J. J. Sun,Michael Tran,Thomas Andre,Syed M. Alam,Francis Poh,J. H. Lee,Yew Tuck Chow,Yi Jiang,Hong-xi Liu,C. C. Wang,Seung-Mo Noh,Taiebeh Tahmasebi,S. K. Ye,Danny Pak-Chum Shum +26 more
TL;DR: An overview of important features for reliable and manufacturable ST-MRAM as well as new results in two areas: pMTJ arrays with data retention sufficient for programming before 260°C wave solder, and performance of a 256Mb, DDR3 ST- MRAM product chip.