J. Jopling

Bio: J. Jopling is an academic researcher from Intel. The author has contributed to research in topics: NMOS logic & Logic gate. The author has an hindex of 5, co-authored 5 publications receiving 1009 citations.

A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

Abstract: A 22nm generation logic technology is described incorporating fully-depleted tri-gate transistors for the first time. These transistors feature a 3rd-generation high-k + metal-gate technology and a 5th generation of channel strain techniques resulting in the highest drive currents yet reported for NMOS and PMOS. The use of tri-gate transistors provides steep subthreshold slopes (∼70mV/dec) and very low DIBL (∼50mV/V). Self-aligned contacts are implemented to eliminate restrictive contact to gate registration requirements. Interconnects feature 9 metal layers with ultra-low-k dielectrics throughout the interconnect stack. High density MIM capacitors using a hafnium based high-k dielectric are provided. The technology is in high volume manufacturing.

High performance 32nm logic technology featuring 2 nd generation high-k + metal gate transistors

Abstract: A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um I off . PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um I off . The impact of SRAM cell and array size on Vccmin is reported.

Erratic fluctuations of sram cache vmin at the 90nm process technology node

Abstract: Erratic bit phenomena have been reported in advanced flash memories, and have been attributed to trapping/detrapping effects that modify the threshold voltage This paper describes for the first time the observance of erratic behavior in SRAM Vmin, defined as the minimum voltage at which the SRAM array is functional Random telegraph signal (RTS) noise in the soft breakdown gate leakage is shown to be the cause The erratic Vmin phenomenon can be eliminated for 90 nm SRAMs by process optimization However, erratic Vmin behavior gets worse with smaller cell sizes and represents another constraint on the scaling of SRAM cells and on the minimum operating voltage of the SRAM array A combination of process and circuit solutions will likely be needed to enable continued SRAM cell scaling

Dielectric breakdown in a 45 nm high-k/metal gate process technology

Abstract: In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology

Abstract: Stress Induced Leakage Current (SILC) has been observed on non-optimized high-K (HK) and metal-gate (MG) transistors. Large NMOS PBTI degradation and correlation to SILC increase on such gate stack is a result of large trap generations in the bulk-HK. This poses a long term reliability concern on product standby power and can limit the operating voltage if not suppressed. On an optimized HK+MG process, we demonstrate that SILC has been suppressed. The transistor level SILC data, model and Product burn-in stress data support this. With optimized process, SILC has no impact on products made of 45nm HK+MG transistors.

Graphene and two-dimensional materials for silicon technology.

Abstract: The development of silicon semiconductor technology has produced breakthroughs in electronics—from the microprocessor in the late 1960s to early 1970s, to automation, computers and smartphones—by downscaling the physical size of devices and wires to the nanometre regime. Now, graphene and related two-dimensional (2D) materials offer prospects of unprecedented advances in device performance at the atomic limit, and a synergistic combination of 2D materials with silicon chips promises a heterogeneous platform to deliver massively enhanced potential based on silicon technology. Integration is achieved via three-dimensional monolithic construction of multifunctional high-rise 2D silicon chips, enabling enhanced performance by exploiting the vertical direction and the functional diversification of the silicon platform for applications in opto-electronics and sensing. Here we review the opportunities, progress and challenges of integrating atomically thin materials with silicon-based nanosystems, and also consider the prospects for computational and non-computational applications. Progress in integrating atomically thin two-dimensional materials with silicon-based technology is reviewed, together with the associated opportunities and challenges, and a roadmap for future applications is presented.

Considerations for Ultimate CMOS Scaling

Abstract: This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking

Abstract: Multiple logic devices are presently under study within the Nanoelectronic Research Initiative (NRI) to carry the development of integrated circuits beyond the complementary metal-oxide-semiconductor (CMOS) roadmap. Structure and operational principles of these devices are described. Theories used for benchmarking these devices are overviewed, and a general methodology is described for consistent estimates of the circuit area, switching time, and energy. The results of the comparison of the NRI logic devices using these benchmarks are presented.

Attosecond metrology: from electron capture to future signal processing

Abstract: The accurate measurement of time lies at the heart of experimental science, and is relevant to everyday life. Extending chronoscopy to ever shorter timescales has been the key to gaining real-time insights into microscopic phenomena, ranging from vital biological processes to the dynamics underlying high technologies. The generation of isolated attosecond pulses in 2001 allowed the fastest of all motions outside the nucleus — electron dynamics in atomic systems — to be captured. Attosecond metrology has provided access to several hitherto immeasurably fast electron phenomena in atoms, molecules and solids. The fundamental importance of electron processes for the physical and life sciences, technology and medicine has rendered the young field of attosecond science one of the most dynamically expanding research fields of the new millennium. Here, we review the basic concepts underlying attosecond measurement and control techniques. Among their many potential applications, we focus on the exploration of the fundamental speed limit of electronic signal processing. This endeavour relies on ultimate-speed electron metrology, as provided by attosecond technology. This article reviews the basic concepts underlying attosecond measurement and control techniques. Emphasis is given to exploring the fundamental speed limit of electronic signal processing that employs ultimate-speed electron metrology provided by attosecond technology.

Improved Contacts to MoS2 Transistors by Ultra-High Vacuum Metal Deposition

Abstract: The scaling of transistors to sub-10 nm dimensions is strongly limited by their contact resistance (RC). Here we present a systematic study of scaling MoS2 devices and contacts with varying electrode metals and controlled deposition conditions, over a wide range of temperatures (80 to 500 K), carrier densities (1012 to 1013 cm–2), and contact dimensions (20 to 500 nm). We uncover that Au deposited in ultra-high vacuum (∼10–9 Torr) yields three times lower RC than under normal conditions, reaching 740 Ω·μm and specific contact resistivity 3 × 10–7 Ω·cm2, stable for over four months. Modeling reveals separate RC contributions from the Schottky barrier and the series access resistance, providing key insights on how to further improve scaling of MoS2 contacts and transistor dimensions. The contact transfer length is ∼35 nm at 300 K, which is verified experimentally using devices with 20 nm contacts and 70 nm contact pitch (CP), equivalent to the “14 nm” technology node.