J. Lewis

Bio: J. Lewis is an academic researcher from Texas Instruments. The author has contributed to research in topics: Low-power electronics & Fault coverage. The author has an hindex of 1, co-authored 1 publications receiving 281 citations.

Minimizing power consumption in scan testing: pattern generation and DFT techniques

Abstract: It is a well-known phenomenon that test power consumption may exceed that of functional operation. ICs have been observed to fail at specified minimum operating voltages during structured at-speed testing while passing all other forms of test. Methods exist to reduce power without dramatically increasing pattern volume for a given coverage. We present case study information on ATPG- and DFT-based solutions for test power reduction.

Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs

Abstract: When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests This paper presents a scalable approach called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method

Power Supply Noise in SoCs: Metrics, Management, and Measurement

Abstract: Power integrity is emerging as a major challenge in deep-submicron SoC designs. The lack of predictability is complicating timing closure, physical design, production test, and speed grading of SoCs. This article describes and validates two metrics that quantify the impact of power supply noise. The IC industry is moving quickly to adopt new deep-submicron (DSM) technologies that offer unprecedented integration levels and cost benefits. These advanced technologies pose unexpected challenges to the semiconductor industry. The DSM problems have led the development of SOC design methodologies to deal with the problem of complexity and productivity. To reduce power dissipation, manufacturers have scaled down supply voltage in each successive technology. Designers analyzed power supply noise with static voltage drop (SVD) analysis, which might not reflect the true nature of power supply fluctuations. Dynamic voltage drop (DVD) analysis is emerging as a replacement of SVD analysis for capturing the impact of power supply noise on the timing behavior of logic and memory cells.

Power-aware test: Challenges and solutions

Abstract: Power-aware test is increasingly becoming a major manufacturing test consideration due to the problems of increased power dissipation in various test modes as well as test implications that arise due to the usage of various low-power design technologies in devices today. Several challenges emerge for test engineers and test tool developers, including (and not restricted to) understanding of various concerns associated with power-aware test, development of power-aware design-for-test (DFT), automatic test pattern generation (ATPG) techniques, and test power analysis flows, evaluation of their efficacy and ensuring easy/rapid deployment. This paper highlights concerns and challenges in power-aware test, surveys various practices drawn from both academia and industry, and points out critical gaps that need to be addressed in the future.

On reducing peak current and power during test

Abstract: This paper presents a progressive match filling (PMF) technique to reduce the peak current and power dissipation during the fast capture cycle in broadside delay fault testing. The proposed method fills the unspecified values (X) in the generated initialization vector such that the resulting launch vector at a minimal Hamming distance from the initialization vector. The proposed method does not require any hardware modification and can be used to obtain any test sets that require two pattern tests. Experimental results show that the proposed method reduces the peak current and power dissipation during the fast capture cycle by 40.59% on average and up to 54.17% for large ISC AS 89 circuits.

On generating pseudo-functional delay fault tests for scan designs

Abstract: In designs using DFT, such as scan, some of the faults that are untestable in the circuit without DFT become testable after DFT insertion. Additionally, scan tests may scan in illegal or unreachable states that cause nonfunctional operation of the circuit during test. This may cause higher than normal power dissipation and demands on supply current. We propose new techniques to determine illegal states of circuits that can be used during ATPG to prohibit tests using such states. The resulting tests are essentially functional or pseudofunctional.