Signal Integrity Simplified

La recuperation d’energie est un theme de recherche prometteur qui explore un large eventail de sources. Parmi ces sources, on trouve l’energie mecanique, thermique, electromagnetique, etc. Cette these se propose d’explorer des solutions techniques de recuperation de l’energie electromagnetique ambiante. Ce type d’energie offre une belle opportunite pour participer a l’alimentation, partielle ou complete, d’un systeme de communication sans fil a basse consommation. Beaucoup d’applications interessantes telles que les reseaux de capteurs sans fil (WSN), assurant ainsi l’IoT (internet of things), dans le domaine medical et dans la securite, sont dotes d’une antenne. Or cette antenne qui est un composant passif volumineux n’est utilisee qu’une faible fraction du temps pour les seules communications. Dans le cadre de la recuperation d’energie RF, l’idee est de mettre a profit ce composant pour glaner l’energie electromagnetique ambiante, malgre la faible puissance recuperee. Associee a l’antenne, la recuperation d’energie RF est basee sur la mise en œuvre de diodes en redresseurs. Dans ce manuscrit, des diodes integrees issues d’une technologie moderne : FDSOI 28 nm sont utilisees.A l’issue de ces travaux, trois « runs » dont deux en technologie FDSOI ont pu etre realises. Des convertisseurs d’energie RF, du type Dickson, d’un et deux etages, ont ete concus et realises a l’aide de cette technologie, mesures et meme compares a des convertisseurs RF-DC realises avec une autre technologie BiCMOS 55 nm. Les convertisseurs realises sont a l’etat de l’art au niveau du rendement de conversion energetique pour une puissance donnee de l’ordre de -20 dBm. La technologie FD-SOI offre un nouveau degre de liberte a l’aide de la polarisation de la grille arriere (BG : Back Gate). Cette polarisation du BG permet de modifier les parametres de l’element non-lineaire a la base de la conversion. Par ailleurs, une etude sur la realisation d’une diode Schottky integree dans le processus de la FDSOI 28 nm a meme ete envisagee. A l’issue de ces premieres experiences, une methode d’optimisation de la conception de ces convertisseurs Dickson a partir d’un cahier des charges simplifiee, a ete proposee.

https://tel.archives-ouvertes.fr/tel-01979987/document

Conception d'un circuit electonique pour la récupération d'énergie électromagnétique en technologie FDSOI 28 nm

As model size and the number of layers increase, Deep Neural Networks (DNNs) demand enormous computational power and throughput to meet exceedingly high prediction accuracy’s of today’s machine learning (ML) applications. Spatial hardware accelerators have been proposed that optimize the dataflow and exploit sparsity to provide a significant decrease in power consumption. As spatial architectures are traditionally designed with metallic interconnects, significant power is expended for data movement for different dataflows. In this paper, we exploit extended wireless technology to design a power-efficient and high-throughput DNN accelerator, e-WiNN, that can be configured for all representative dataflows and arithmetic precisions. We leverage novel circuit design by utilizing Dadda-algorithm based Multiply-and-Accumulate (MAC) circuits for 4-bit, 8-bit and 16-bit inputs to reduce area, power and delay constraints in 14 nm predictive technology. Our novel wireless transmitter integrates on- off keying (OOK) modulator with power amplifier that results in significant energy savings. To reduce the area overhead, we cluster wireless transceivers into groups of four such that both weights and input features can be effectively multicast to reduce the data movement. The energy efficient transceiver circuit is implemented in state-of-the-art BSIM 32 nm FinFET technology model and our link budget considers required RF power for different frequencies and inter-PE distance at three different antenna directivities including isotropic. Our detailed RTL modeling and cycle-accurate simulation results show that e-WiNN achieves 36.3% latency reduction and 76.1% energy saving when compared to state-of-art wire interconnected accelerators; 70.3% area reduction and 41.6% energy saving at the cost of 11% latency increase when compared to prior wireless accelerators on various neural networks (AlexNet, VGG16, and ResNet-9/50).

Exploiting Wireless Technology for Energy-Efficient Accelerators With Multiple Dataflows and Precision

This paper reviews recent developments in design of antennas and impedance matching networks for RF Energy Harvesting (RF-EH) at UHF. The antenna design is considered in conjunction with the requirements that it places on the impedance matching network (IMN), in order to match the load which is an RF to DC converter. It is shown that there may be advantages in using an interface impedance between the antenna and the IMN that differs from the conventional 50 Ω impedance. Various options are considered for the design of an IMN driving a rectifier load. A novel adaptive IMN architecture is proposed that can match two different load impedances, depending on the received power level. This can optimize Power Conversion Efficiency (PCE) over a range of different input powers that may be encountered in RF EH.

Design Considerations of Antennas and Adaptive Impedance Matching Networks for RF Energy Harvesting

Les systemes de telecommunications actuels necessitent des filtres passe bande fonctionnant a des frequences comprises entre 1 GHz et 10 GHz pour les systemes les plus repandus, notamment la telephonie mobile. Les filtres actuels sont reportes, donc non integres sur silicium. Ils presentent certains inconvenients : cout, place occupee, incompatibilite avec les technologies silicium…Une solution consiste a utiliser des resonateurs a ondes de volume, plus communement appeles BAW (Bulk Acoustic Waves). Ils presentent l'avantage d'etre integrables sur silicium. De nouvelles architectures nommees CRF (Coupled Resonator Filter) font appel a des resonateurs a ondes de volume (BAW) mais aussi a des structures utilisant des couplages acoustiques entre differentes couches. L'objectif du travail propose est de modeliser les structures actuelles et en cours d'etudes pour obtenir des modeles de type circuits electriques. Ces modeles seront valides par des mesures effectuees au laboratoire sur des resonateurs BAW et sur des filtres qui sont realises par nos partenaires. La premiere partie des etudes portait sur le comportement RF sous faible et forte puissances, suivi du developpement d’un modele large bande simule sous ADS decrivant le comportement des filtres BAW sous faible et forte puissances. Une optimisation du temps de mesure en frequence est effectuee pour reduire le temps du test RF. La seconde partie de la these est orientee vers le developpement d'une nouvelle methode de test pseudo-temporelle des filtres hyperfrequences qui consiste a mesurer directement leur impact sur un signal numerique grâce au parametre «EVM» (Error Vector Magnitude). Ce parametre est relie au BER et nos travaux montrent qu’il permet egalement de retrouver en partie les parametres S et detecter les filtres defaillants a partir d’une seule mesure. Cette nouvelle technique permettant le test de filtres a partir d’un seul point de mesure permet de reduire le temps et le cout de caracterisation a des fins industrielles. Ce travail s'est deroule dans un cadre de collaborations avec le LETI et STMicroelectronics au sein du projet FAST labellise par le pole MINALOGIC.

https://tel.archives-ouvertes.fr/tel-00639427/document

Modélisation et caractérisation linéaire et non linéaire des filtres RF en technologie BAW et CRF et méthode pseudo-temporelle de test industriel

In the context of the radio frequency energy harvesting, RF-DC converter based on a one stage Dickson voltage rectifier has been studied and realized in 28 nm FD-SOI technology. After the analysis of the operating constraints of the circuit, a choice was made on the N-low threshold voltage transistor (NLVT). Moreover, the back gate polarization (BGP) effect, on circuit performance, has been analyzed and a dynamic BGP is proposed which improve rectifier performance.

Design of Dickson rectifier for RF energy harvesting in 28 nm FD-SOI technology

Electronic circuit design for RF energy harvesting using 28 nm FD‐SOI technology

In this article, two stages of the Dickson voltage rectifier are realized in two different technologies: FD-SOI 28 nm and BiCMOS 55 nm. The measurement of I-V characteristics of diodes in both technologies reveals that FD-SOI manifests a smaller threshold voltage and less leakage current compared to BiCMOS. It is also ascertained through the measurement results that the efficiency of the rectifier realized with the FD-SOI is better than that of rectifier obtained using BiCMOS. Furthermore, the impact of back gate polarization (BGP) in FD-SOI is investigated and a novel dynamic BGP is proposed. Power conversion efficiency (PCE) of 45 % is achieved at −10 dBm in FD-SOI, whereas, a PCE of 36 % is observed in BiCMOS at the same power.

https://ieeexplore.ieee.org/iel7/8417183/8439129/08439412.pdf

Performance Comparison of Two Stage of Dickson Voltage Rectifier Realized in FD-SOI 28 nm and BiCMOS 55 nm for RF Energy Harvesting

Etude d'une méthodologie de caractérisation de filtres CRF à grande échelle

This work introduces high-frequency inter-chip links. This approach is proposed to connect two chiplets on a silicon interposer at high speed; it can be used for either active or passive silicon interposer. This approach is suggested to support the increasing need for higher data rates and larger bandwidths among different components such as CPU/GPU to memory. To limit the distortion of the signal, we use a 60-GHz carrier to transmit in the propagating LC region of the wires. This significantly reduces the signal distortion as compared to base band communications working in the RC region. Furthermore, we used duobinary modulation to achieve higher bandwidth per channel, this modulation having the same spectral efficiency as PAM-4 without the need for extra comparators. Hereafter, we simulated a 7-mm long interposer channel using 3D EM tool, we used 28-nm FD-SOI technology for the chiplets, and BiCMOS 130 nm back-end-of-line for the interposer channel, both technologies being from STMicroelectronics. For a proof-of-concept, simulation results using a transmitter and receiver in 28-nm FD-SOI technology are shown.

J.-M. Duchamp

Papers

Design of Dickson rectifier for RF energy harvesting in 28 nm FD-SOI technology

Electronic circuit design for RF energy harvesting using 28 nm FD‐SOI technology

Performance Comparison of Two Stage of Dickson Voltage Rectifier Realized in FD-SOI 28 nm and BiCMOS 55 nm for RF Energy Harvesting

Etude d'une méthodologie de caractérisation de filtres CRF à grande échelle

7-mm low-latency inter-chiplet serial link with silicon interposer