The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the forthcoming STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on the Cell full system simulator. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

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The potential of the cell processor for scientific computing

Roadrunner is a 1.38 Pflop/s-peak (double precision) hybrid-architecture supercomputer developed by LANL and IBM. It contains 12,240 IBM PowerXCell 8i processors and 12,240 AMD Opteron cores in 3,060 compute nodes. Roadrunner is the first supercomputer to run Linpack at a sustained speed in excess of 1 Pflop/s. In this paper we present a detailed architectural description of Roadrunner and a detailed performance analysis of the system. A case study of optimizing the MPI-based application Sweep3D to exploit Roadrunner's hybrid architecture is also included. The performance of Sweep3D is compared to that of the code on a previous implementation of the Cell Broadband Engine architecture---the Cell BE---and on multi-core processors. Using validated performance models combined with Roadrunner-specific microbenchmarks we identify performance issues in the early pre-delivery system and infer how well the final Roadrunner configuration will perform once the system software stack has matured.

Entering the petaflop era: the architecture and performance of Roadrunner

Node level heterogeneous architectures have become attractive during the last decade for several reasons: compared to traditional symmetric CPUs, they offer high peak performance and are energy and/or cost efficient. With the increase of fine-grained parallelism in high-performance computing, as well as the introduction of parallelism in workstations, there is an acute need for a good overview and understanding of these architectures. We give an overview of the state-of-the-art in heterogeneous computing, focusing on three commonly found architectures: the Cell Broadband Engine Architecture, graphics processing units (GPUs), and field programmable gate arrays (FPGAs). We present a review of hardware, available software tools, and an overview of state-of-the-art techniques and algorithms. Furthermore, we present a qualitative and quantitative comparison of the architectures, and give our view on the future of heterogeneous computing.

/pdf/state-of-the-art-in-heterogeneous-computing-1k2hcnpa4d.pdf

State-of-the-art in heterogeneous computing

Для числа ε > 0 и вещественной функции f на отрезке [a, b] обозначим через N(ε, f, [a, b]) супремум множества тех номеров n, для которых в [a, b] существует набор неналегающих отрезков [ai, bi], i = 1, . . . , n, таких, что |f(ai)− f(bi)| > ε для всех i = 1, . . . , n (sup ∅ = 0). Доказана следующая теорема: если {fj} – поточечно ограниченная последовательность вещественных функций на отрезке [a, b] такая, что n(ε) ≡ lim supj→∞N(ε, fj , [a, b]) < ∞ для любого ε > 0, то {fj} содержит подпоследовательность, которая всюду на [a, b] сходится к некоторой функции f такой, что N(ε, f, [a, b]) 6 n(ε) при любом ε > 0. Показано, что основное условие в этой теореме, связанное с верхним пределом, необходимо для равномерно сходящейся последовательности {fj} и “почти” необходимо для всюду сходящейся последовательности измеримых функций и что многие поточечные принципы выбора, обобщающие классическую теорему Хелли, вытекают из этой теоремы, а также приводятся примеры, иллюстрирующие ее точность. Библиография: 16 названий.

Место и роль инновационных технологий на уроках математики

As the computational power of GPUs continues to scale with Moore's Law, an increasing number of applications are becoming limited by memory bandwidth. We propose an approach for programming GPUs with tightly-coupled specialized DMA warps for performing memory transfers between on-chip and off-chip memories. Separate DMA warps improve memory bandwidth utilization by better exploiting available memory-level parallelism and by leveraging efficient inter-warp producer-consumer synchronization mechanisms. DMA warps also improve programmer productivity by decoupling the need for thread array shapes to match data layout. To illustrate the benefits of this approach, we present an extensible API, CudaDMA, that encapsulates synchronization and common sequential and strided data transfer patterns. Using CudaDMA, we demonstrate speedup of up to 1.37x on representative synthetic micro-benchmarks, and 1.15x–3.2x on several kernels from scientific applications written in CUDA running on NVIDIA Fermi GPUs.

https://ppl.stanford.edu/papers/sc11-bauer-slides.pdf

CudaDMA: optimizing GPU memory bandwidth via warp specialization

The Cell Broadband Engine™ (Cell/B.E.) processor is the first implementation of the Cell Broadband Engine Architecture (CBEA), developed jointly by Sony, Toshiba, and IBM. In addition to use of the Cell/B.E. processor in the Sony Computer Entertainment PLAYSTATION® 3 system, there is much interest in using it for workstations, media-rich electronics devices, and video and image processing systems. The Cell/B.E. processor includes one PowerPC® processor element (PPE) and eight synergistic processor elements (SPEs). The CBEA is designed to be well suited for a wide variety of programming models, and it allows for partitioning of work between the PPE and the eight SPEs. In this paper we show that the Cell/B.E. processor can outperform other modern processors by approximately an order of magnitude and by even more in some cases.

Cell broadband engine architecture and its first implementation: a performance view

For systems that use hardware accelerators to combine multicore and multiprocess technology with libraries and computational kernels, the drawbacks are the complexity of the programming model and the corresponding verification of the software and validation of the system performance capabilities. In this paper, we describe a software approach to utilizing the compute power of the Cell Broadband Engine® processor and a cluster composed of x86-64 and IBM PowerXCell™ 8i processors integrated within a single hybrid compute node. We review past approaches to provide motivation for our development of the Data Communication and Synchronization (DaCS) library and Accelerated Library Framework (ALF), which enable developers to create new applications and adapt existing applications to exploit hybrid computing platforms. We follow with examples of porting existing x86-64 processor-based applications to the hybrid cluster platform in order to demonstrate the capabilities of ALF and DaCS and discuss how one application was extended to become a stress and performance test for various system components. Finally, we present the applicability of this programming model, accelerator design, and test architecture to other system architectures, applications, and workload segments.

J. N. Dale

Papers

Cell broadband engine architecture and its first implementation: a performance view

Software architecture and system validation of an open, unified model for accelerated multicore computing