J.R. Schwank

Bio: J.R. Schwank is an academic researcher from Sandia National Laboratories. The author has contributed to research in topics: Silicon on insulator & Irradiation. The author has an hindex of 54, co-authored 169 publications receiving 8997 citations.

Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices

Abstract: We have identified several features of the 1/f noise and radiation response of metal‐oxide‐semiconductor (MOS) devices that are difficult to explain with standard defect models. To address this issue, and in response to ambiguities in the literature, we have developed a revised nomenclature for defects in MOS devices that clearly distinguishes the language used to describe the physical location of defects from that used to describe their electrical response. In this nomenclature, ‘‘oxide traps’’ are simply defects in the SiO2 layer of the MOS structure, and ‘‘interface traps’’ are defects at the Si/SiO2 interface. Nothing is presumed about how either type of defect communicates with the underlying Si. Electrically, ‘‘fixed states’’ are defined as trap levels that do not communicate with the Si on the time scale of the measurements, but ‘‘switching states’’ can exchange charge with the Si. Fixed states presumably are oxide traps in most types of measurements, but switching states can either be interface tr...

Radiation effects in SOI technologies

Abstract: Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Device modeling of ferroelectric capacitors

Abstract: A physically based methodology is developed for modeling the behavior of electrical circuits containing nonideal ferroelectric capacitors. The methodology is illustrated by modeling the discrete ferroelectric capacitor as a stacked dielectric structure, with switching ferroelectric and nonswitching dielectric layers. Electrical properties of a modified Sawyer–Tower circuit are predicted by the model. Distortions of hysteresis loops due to resistive losses as a function of input signal frequency are accurately predicted by the model. The effect of signal amplitude variations predicted by the model also agree with experimental data. The model is used as a diagnostic tool to demonstrate that cycling degradation, at least for the sample investigated, cannot be modeled by the formation of nonswitching dielectric layer(s) or the formation of conductive regions near the electrodes, but is consistent with a spatially uniform reduction in the number of switching dipoles.

Production and propagation of single-event transients in high-speed digital logic ICs

Abstract: The production and propagation of single-event transients in scaled metal oxide semiconductor (CMOS) digital logic circuits are examined. Scaling trends to the 100-nm technology node are explored using three-dimensional mixed-level simulations, including both bulk CMOS and silicon-on-insulator (SOI) technologies. Significant transients in deep submicron circuits are predicted for particle strikes with linear energy transfer as low as 2 MeV-cm/sup 2//mg, and unattenuated propagation of such transients can occur in bulk CMOS circuits at the 100-nm technology node. Transients approaching 1 ns in duration are predicted in bulk CMOS circuits. Body-tied SOI circuits produce much shorter transients than their bulk counterparts, making them more amenable to transient filtering schemes based on temporal redundancy. Body-tied SOI circuits also maintain a significant advantage in single-event transient immunity with scaling.

Current and Future Challenges in Radiation Effects on CMOS Electronics

Abstract: Advances in microelectronics performance and density continue to be fueled by the engine of Moore's law. Although lately this engine appears to be running out of steam, recent developments in advanced technologies have brought about a number of challenges and opportunities for their use in radiation environments. For example, while many advanced CMOS technologies have generally shown improving total dose tolerance, single-event effects continue to be a serious concern for highly scaled technologies. In this paper, we examine the impact of recent developments and the challenges they present to the radiation effects community. Topics covered include the impact of technology scaling on radiation response and technology challenges for both total dose and single-event effects. We include challenges for hardening and mitigation techniques at the nanometer scale. Recent developments leading to hardness assurance challenges are covered. Finally, we discuss future radiation effects challenges as the electronics industry looks beyond Moore's law to alternatives to traditional CMOS technologies.

Physics of thin-film ferroelectric oxides

Abstract: This review covers important advances in recent years in the physics of thin-film ferroelectric oxides, the strongest emphasis being on those aspects particular to ferroelectrics in thin-film form. The authors introduce the current state of development in the application of ferroelectric thin films for electronic devices and discuss the physics relevant for the performance and failure of these devices. Following this the review covers the enormous progress that has been made in the first-principles computational approach to understanding ferroelectrics. The authors then discuss in detail the important role that strain plays in determining the properties of epitaxial thin ferroelectric films. Finally, this review ends with a look at the emerging possibilities for nanoscale ferroelectrics, with particular emphasis on ferroelectrics in nonconventional nanoscale geometries.

Ferroelectric, dielectric and piezoelectric properties of ferroelectric thin films and ceramics

Abstract: Ferroelectric, dielectric and piezoelectric properties of ferroelectric thin films and ceramics are reviewed with the aim of providing an insight into different processes which may affect the behaviour of ferroelectric devices, such as ferroelectric memories and micro-electro-mechanical systems. Taking into consideration recent advances in this field, topics such as polarization switching, polarization fatigue, effects of defects, depletion layers, and depolarization fields on hysteresis loop behaviour, and contributions of domain-wall displacement to dielectric and piezoelectric properties are discussed. An introduction into dielectric, pyroelectric, piezoelectric and elastic properties of ferroelectric materials, symmetry considerations, coupling of electro-mechanical and thermal properties, and definitions of relevant ferroelectric phenomena are provided.

Radiation-induced soft errors in advanced semiconductor technologies

Abstract: The once-ephemeral radiation-induced soft error has become a key threat to advanced commercial electronic components and systems. Left unchallenged, soft errors have the potential for inducing the highest failure rate of all other reliability mechanisms combined. This article briefly reviews the types of failure modes for soft errors, the three dominant radiation mechanisms responsible for creating soft errors in terrestrial applications, and how these soft errors are generated by the collection of radiation-induced charge. The soft error sensitivity as a function of technology scaling for various memory and logic components is then presented with a consideration of which applications are most likely to require soft error mitigation.

Status of silicon carbide (SiC) as a wide-bandgap semiconductor for high-temperature applications: A review

Abstract: Silicon carbide (SiC), a material long known with potential for high-temperature, high-power, high-frequency, and radiation hardened applications, has emerged as the most mature of the wide-bandgap (2.0 eV ≲ Eg ≲ 7.0 eV) semiconductors since the release of commercial 6HSiC bulk substrates in 1991 and 4HSiC substrates in 1994. Following a brief introduction to SiC material properties, the status of SiC in terms of bulk crystal growth, unit device fabrication processes, device performance, circuits and sensors is discussed. Emphasis is placed upon demonstrated high-temperature applications, such as power transistors and rectifiers, turbine engine combustion monitoring, temperature sensors, analog and digital circuitry, flame detectors, and accelerometers. While individual device performances have been impressive (e.g. 4HSiC MESFETs with fmax of 42 GHz and over 2.8 W mm−1 power density; 4HSiC static induction transistors with 225 W power output at 600 MHz, 47% power added efficiency (PAE), and 200 V forward blocking voltage), material defects in SiC, in particular micropipe defects, remain the primary impediment to wide-spread application in commercial markets. Micropipe defect densities have been reduced from near the 1000 cm−2 order of magnitude in 1992 to 3.5 cm−2 at the research level in 1995.

Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Abstract: We present an overview of negative bias temperature instability (NBTI) commonly observed in p-channel metal–oxide–semiconductor field-effect transistors when stressed with negative gate voltages at elevated temperatures. We discuss the results of such stress on device and circuit performance and review interface traps and oxide charges, their origin, present understanding, and changes due to NBTI. Next we discuss the effects of varying parameters (hydrogen, deuterium, nitrogen, nitride, water, fluorine, boron, gate material, holes, temperature, electric field, and gate length) on NBTI. We conclude with the present understanding of NBTI and its minimization.