J. Sklansky

Bio: J. Sklansky is an academic researcher from Princeton University. The author has contributed to research in topics: Markov model & Realizability. The author has an hindex of 2, co-authored 2 publications receiving 36 citations.

General Synthesis of Tributary Switching Networks

Abstract: A synthesis procedure is described which generates all tributary networks (TRIBs) realizing a given truth function when no a priori assignment of the variables to input terminals is specified. If the truth function is not known to be realizable by a TRIB structure, the synthesis procedure provides a convenient test for TRIB realizability. If the variables are preassigned to input terminals, the synthesis and test are still applicable and correspondingly shorter. A major tool of the procedure is the matrix of binary representations of the minterms of the truth function?the so called ``minterm matrix.'' The procedure is illustrated by a numerical example.

A Survey of Microcellular Research

Abstract: This paper is a survey of research on microcellular techniques. Of particular interest are those techniques that are appropriate for realization by modern batch-fabrication processes, since the rapid emergence of reliable and economical batch-fabricated components represents probably the most important current trend in the field of digital circuits.First the manufacturing methods for batch-fabricated components are reviewed, and the advantages to be realized from the application of the principles of cellular logic design are discussed. Also two categorizations of cellular arrays are made in terms of the complexity of each cell (only low-complexity cells are considered) and in terms of the various application areas.After a survey of very early techniques that can be viewed as exemplifying cellular approaches, modern-day cellular arrays are discussed on the basis of whether they are fixed cell-function arrays or variable cell-function arrays. In the fixed cell-function arrays the switching function produced by each cell is fixed; the cell parameters are used only in the modification of the interconnection structure. Several versions of NOR gate arrays, majority gate arrays, adder arrays, and others are reviewed in terms of synthesis techniques and array growth rates.Similarly, the current status of research is summarized in variable cell-function arrays, where not only the interconnection structure but also the function produced by each cell is determined by parameter selection. These arrays include various general function cascades, outpoint arrays, and cobweb arrays, for example. Again, the various cell types that have been considered are pointed out, as well as synthesis procedures and growth rates appropriate for them.Finally, several areas requiring further research effort are summarized. These include the need for more realistic measures of array growth rates, the need for synthesis techniques for multiple-function arrays and programmable arrays, and the need for fault-avoidance algorithms in integrated structures.

Cutpoint Cellular Logic

Abstract: A cutpoint cellular array is a two-dimensional rectangular arrangement of square cells, each of which has binary inputs on the top and left edges and outputs on the bottom and right edges. Each cell is interconnected with neighboring cells, and it is specialized by a set of binary constants that are termed cutpoints. This paper is concerned with the choice of the logical properties for each cutpoint cell, so that an array of these cells is capable of efficient and general combinational and sequential logic. Logical design algorithms are given, as well as a number of actual designs. It is believed that cutpoint cellular arrays have promise for application in the manufacture of a large number of integrated circuit components on one substrate.

Cellular logic architectures for optical computers.

Abstract: A general approach is described for optically implementing massively parallel logic. Cellular array logic and the cellular automaton theory are emphasized as a guiding principle in the design of optical parallel computers. These theoretical methods are important clues to elucidate the general characteristics and the limitation of optical parallel logic. We propose three architectures for optical computing systems: the optical Minnick cellular logic array for logical function synthesis, the local cellular logic based on the holographic filter synthesis, and the table lookup architecture using a matched filter array for binary data processing. A close relationship between the table lookup architecture and the symbolic substitution and the content-addressable memory is pointed out.

Unate Cellular Logic

Abstract: A fundamental problem in "cellular logic" is to be able to "synthesize" "cellular arrays" for arbitrary switching functions that minimize a set of design parameters like size of the arrays and complexity of the individual cells and of the interconnection pattern on the cells. This paper is an attempt to develop "minimization algorithms for cellular arrays."

Canonical Form and Synthesis of Cellular Cascades

Abstract: Cascades of two-input, one-output general function cells have been studied previously with the restriction that no external variable may drive more than one cell. Upon relaxing this restriction, it is shown that a variable that drives more than one cell in a cascade need never drive more than one cell that is not an EXCLUSIVE-OR cell, and that cell must be the first cell driven by the variable in the cascade. From this it follows that there exists a canonical form for cellular cascades with repeated inputs. Furthermore, the length of a cascade required to produce an n-variable function is bounded by (n2+n-4)/2, and there are functions that meet this bound for all n. Derived from knowledge of the canonical form, a realizability and synthesis algorithm is described that is an extension of previously described algorithms. The algorithm has been used to test the 402 Harvard functions, and a table of minimal-length cascades of realizable functions is included in the paper. Although the number of realizable functions is greatly increased when the input restriction is relaxed, it is shown that the fraction of n-variable functions that are realizable becomes vanishingly small as n grows large. In particular, for example, of the 2n+1 symmetric functions of n-variables, precisely 12 are realizable for all n?3.