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Author

J.V.R. Ravindra

Bio: J.V.R. Ravindra is an academic researcher from Vardhaman College of Engineering. The author has contributed to research in topics: Multiplier (economics) & Very-large-scale integration. The author has an hindex of 7, co-authored 34 publications receiving 126 citations. Previous affiliations of J.V.R. Ravindra include International Institute of Information Technology & Information Technology Institute.

Papers
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Journal ArticleDOI
TL;DR: FORTIS algorithm has been proposed for generation of sub-keys and the strength of the algorithm against side-channel power attacks is investigated using ChipWhisperer®-Lite and Artix FPGA as target board.

21 citations

Proceedings ArticleDOI
21 May 2006
TL;DR: This paper proposes a novel encoding technique that reduces the switching activity due to capacitive coupling resulting in lower power overhead and results show that the power dissipation in a bus is reduced by about 23% with this encoding technique.
Abstract: In current VLSI technology, interconnects have become the predominant source of power dissipation. Particularly in DSM technology, the spacing between interconnects is very less leading to the dominance of coupling capacitance over self capacitance. In 0.13 /spl mu/m technology, it has been found that 75% of the power consumption is due to the coupling capacitance whereas only 25% is due to self capacitance. Thus, earlier schemes which concentrated on minimizing the substrate capacitances are not valid in these buses. Considering these aspects, this paper proposes a novel encoding technique that reduces the switching activity due to capacitive coupling resulting in lower power overhead. The simulation results show that the power dissipation in a bus is reduced by about 23% with this encoding technique. The encoding and decoding circuits have been designed and the power consumed has been compared with those of other coding schemes.

15 citations

Proceedings ArticleDOI
17 Jan 2006
TL;DR: A modified odd/even bus invert scheme, which reduces the simultaneous switching activity, thereby improving the signal integrity and the performance of the proposed coding scheme has been tested on various benchmarks and it is found that SSN or M(di/dt) is reduced by 28% compared to data transmitted unencoded.
Abstract: In high speed digital circuits, the inductive effect is more dominant compared to capacitive effect. In particular, as the technology is shrinking, the spacing between interconnects becomes less which increases simultaneous switching noise (SSN) or M(di/dt) noise. So earlier methods proposed which concentrate on reducing capacitive effect do not hold good. This paper proposes a modified odd/even bus invert scheme, which reduces the simultaneous switching activity, thereby improving the signal integrity. The performance of the proposed coding scheme has been tested on various benchmarks and it is found that SSN or M(di/dt) is reduced by 28% compared to data transmitted unencoded. The proposed codec has been designed and it has been found that power overhead is 3.3%.

13 citations

Proceedings ArticleDOI
18 Mar 2016
TL;DR: Novel techniques against Leakage Power Analysis (LPA) attack on Dual-Rail Precharge Logic (DDPL) which is a Differential Power analysis (DPA) resistant logic style are proposed and the leakage power and CoD are defined.
Abstract: This paper proposes novel techniques against Leakage Power Analysis (LPA) attack on Dual-Rail Precharge Logic (DDPL) which is a Differential Power Analysis (DPA) resistant logic style. DDPL is first applied with sleep transistors technique and second with Normalization technique by which the Cryptosystem is made LPA resistant. Security metrics used for assessing the proposed logic styles are the leakage power and Coefficient of Deviation (CoD). By analyzing the leakage power traces secret key can be extracted, as the leakage power is data dependent. The leakage power dissipated by the Cryptosystem cannot be avoided completely but it can be reduced by which LPA attack can be avoided. To avoid LPA attack, leakage power should be made independent of data that is getting processed in the Cryptosystem. This paper concentrates on leakage power analysis of DDPL NAND applied with novel techniques and defines the leakage power and CoD. The logic styles are implemented and analyzed using Cadence© GPDK 45nm technology node. In the proposed method sleep transistor technique is applied to DDPL by which the power consumption is double the normal DDPL but the data dependency CoD has been reduced by 20% and with the novel Normalized DDPL technique, power consumption is reduced by 30% and the CoD has been reduced by 89.4% which implies that the power traces are made equal for all the input combinations by which LPA attack can be avoided. The power traces are measured at various temperatures by which dependency of Logic style on temperature i.e., thermal Stability is also studied.

9 citations

Proceedings ArticleDOI
01 Jan 2019
TL;DR: A 4:2 compressors with inexact logic minimization by flipping some of the output bits considering efficiency/accuracy into account is presented, to employ Python TensorFlow in Google Co Laboratory© to Upload.
Abstract: Machine Learning (ML) has been one of the applications of approximate circuits. These circuits, part of approximate computing, can be implemented using either probabilistic pruning or inexact logic minimization. Since low power consumption and smaller silicon area are the critical parameters in portable devices, approximate circuits have been the current topic for discussion. This paper presents a 4:2 compressors with inexact logic minimization by flipping some of the output bits considering efficiency/accuracy into account. The proposed 4:2 compressor has been utilized in an 8 8 Dadda multiplier and average power, area and propagation delay of the architectures have been computed. All the simulations have been performed using spectre simulator of Cadence Design Systems in 45nm technology node. To find the difference between the exact and approximate proposed circuits, error analysis has been performed using MATLAB. The application idea of this paper is to employ Python TensorFlow in Google Co Laboratory© to Upload, download the approximate 4:2 compressor which has been implemented in Cadence Virtuoso.

8 citations


Cited by
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Patent
16 Jan 2009
TL;DR: In this paper, the authors have disclosed the apparatus, systems and methods that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms.
Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

56 citations

Patent
08 Oct 2008
TL;DR: In this article, a method and apparatus for balancing an output load using data bus inversion is disclosed, and one such technique comprises measuring the "balance" of data bits across a data bus (e.g., the number of zero values compared to number of one values in a set of parallel data bits).
Abstract: A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.

36 citations

Patent
07 Dec 2012
TL;DR: In this paper, the authors describe an inter-chip interface configured to receive and process electronic data, which includes a receiver circuit that includes a clock tree, which distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of other clock signals.
Abstract: Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes a clock tree configured to receive a clock signal at a clock tree input. The clock tree distributes a plurality of clock signals delayed from the clock signal such that one or more of the clock signals have a delay different from the delays of the other clock signals. The receiver circuit further includes a plurality of data input latches configured to receive a plurality of data elements over two or more different points in time. This configuration at least partially reduces crosstalk and simultaneous switching output noise.

26 citations

Journal ArticleDOI
TL;DR: A static power analysis adversary can physically force a device to leak more information by controlling its operating environment and furthermore measure these leakages with arbitrary precision by modifying the interval length.
Abstract: The static power consumption of modern CMOS devices has become a substantial concern in the context of the side-channel security of cryptographic hardware. Its continuous growth in nanometer-scaled technologies is not only inconvenient for effective low-power designs but does also create a new target for power analysis adversaries. Additionally, it has to be noted that several of the numerous sources of static power dissipation in CMOS circuits exhibit an exponential dependence on environmental factors which a classical power analysis adversary is in control of. These factors include the operating conditions’ temperature and supply voltage. Furthermore, in the case of clock control, the measurement interval can be adjusted arbitrarily. Our experiments on a 150-nm CMOS ASIC reveal that with respect to the signal-to-noise ratio in static power side-channel analyses, stretching the measurement interval decreases the noise exponentially and even more importantly that raising the working temperature increases the signal exponentially. Control over the supply voltage has a far smaller, but still noticeable, positive impact as well. In summary, a static power analysis adversary can physically force a device to leak more information by controlling its operating environment and furthermore measure these leakages with arbitrary precision by modifying the interval length.

22 citations

Journal ArticleDOI
TL;DR: This article proposes a two-phase technique, which uses the order of the path delay in path pairs to detect HTs, and confirms the efficiency and accuracy of the proposed technique are confirmed by a series of experiments.
Abstract: Many fabrication-less design houses are outsourcing their designs to third-party foundries for fabrication to lower cost. This IC development process, however, raises serious security concerns on Hardware Trojans (HTs). Many design-for-trust techniques have been proposed to detect HTs through observing erroneous output or abnormal side-channel characteristics. Side-channel characteristics such as path delay have been widely used for HT detection and functionality verification, as the changes of the characteristics of the host circuit incurred by the inserted HT can be identified through proper methods.In this article, for the first time, we propose a two-phase technique, which uses the order of the path delay in path pairs to detect HTs. In the design phase, a full-cover path set that covers all the nets of the design is generated; meanwhile, in the set, the relative order of paths in path pairs is determined according to their delay. The order of the paths in path pairs serves as the fingerprint of the design. In the test phase, the actual delay of the paths in the full-cover set is extracted from the fabricated circuits, and the order of paths in path pairs is compared with the fingerprint generated in the design phase. A mismatch between them indicates the existence of HTs. Both process variations and measurement noise are taken into consideration. The efficiency and accuracy of the proposed technique are confirmed by a series of experiments, including the examination of both violated path pairs incurred by HTs and their false alarm rate.

20 citations