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Author

J. W. Ting

Bio: J. W. Ting is an academic researcher from GlobalFoundries. The author has contributed to research in topics: JEDEC memory standards & Computer science. The author has an hindex of 4, co-authored 9 publications receiving 115 citations.

Papers
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Proceedings ArticleDOI
01 Dec 2019
TL;DR: In this paper, a manufacturable 22nm FD-SOI 40Mb embedded MRAM (eMRAM) was demonstrated to achieve product functionality and reliability at package level across industrial-grade operating temperature range (−40 to 125 °C) with ECC-off mode.
Abstract: We demonstrate the manufacturable 22nm FD-SOI 40Mb embedded MRAM (eMRAM), by achieving product functionality and reliability at package level across industrial-grade operating temperature range (−40 to 125 °C) with ECC-off mode. The magnetic tunnel junction stack, integration and etch processes were optimized to achieve superior MTJ performances to meet all product requirements. From package level data, we confirmed the product reliability by passing LTOL, HTOL, 1M endurance cycling and 5x solder reflows tests with failure rate < 1 ppm. In addition, we demonstrate the eMRAM capability to cover stand-by magnetic immunity of ~ 600 Oe at 105 °C for 10 years and active-mode magnetic immunity of ~500 Oe.

47 citations

Proceedings ArticleDOI
01 Jun 2017
TL;DR: An unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array with full array functionality, process uniformity and reliability, and 10 years data retention at 125C with extended endurance to ∼ 107 cycles is presented.
Abstract: Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array. Key features are full array functionality with low BER (bit error rate), process uniformity and reliability, 10 years data retention at 125C with extended endurance to ∼ 107 cycles. All achieved with standard BEOL process temperatures. Data retention post 260°C solder reflow temperature cycle is demonstrated.

43 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: 22-nm FD-SOI 40Mb embedded MRAM (eMRAM) macros for automotive-grade-l (Auto-G1) MCU applications are demonstrated and the effects of magnetic tunnel junction (MTJ) size on reliability and scalability of eMRAM technology beyond 22 nm are examined.
Abstract: We demonstrate 22-nm FD-SOI 40Mb embedded MRAM (eMRAM) macros for automotive-grade-l (Auto-G1) MCU applications, highlighting sub-ppm to bit error rate and zero failure after 1M endurance cycles across Auto-G1 operating temperature range (-40∼150 °C). Read disturbance characterization with external field also reveals that 40Mb eMRAM macro is capable of active-mode magnetic immunity > 500 Oe at 150 °C. In addition, based on 22-nm eMRAM macro data, we review the effects of magnetic tunnel junction (MTJ) size on reliability and examine scalability of eMRAM technology beyond 22 nm.

28 citations

Proceedings ArticleDOI
18 Jun 2018
TL;DR: A fully functional embedded MRAM macro integrated into a 22-nm FD-SOI CMOS platform and showing intrinsic stand-by magnetic immunity of 1.4 kOe reveals that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.
Abstract: We demonstrate a fully functional embedded MRAM (eMRAM) macro integrated into a 22-nm FD-SOI CMOS platform. This macro combined with eFlash-flavor MTJ film stacks shows median-die bit error rate (BER) < 1 ppm after 5× solder reflows. It also meets the automotive grade-1 data retention requirement and shows intrinsic stand-by magnetic immunity of 1.4 kOe (BER criteria = 1 ppm) after 1-hr exposure at 25 °C. The results reveal that eMRAM is capable of serving a broad spectrum of eFlash applications at 22 nm or beyond.

24 citations

Proceedings ArticleDOI
12 Dec 2020
TL;DR: In this paper, the authors demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications.
Abstract: We demonstrate highly reliable and mass-production ready 22nm FD-SOI 40Mb embedded-MRAM for industrial-grade (-40~125°C) applications. This technology having 5x solder reflows compatibility stack has passed JEDEC standard qualification (ECC-OFF) with total reliability failures below the product life-time bit-failure-rate requirement for industrial-grade. Using design-process co-optimization, we show the extended performance to meet -40~150°C product operation for Auto-Grade-1 applications with stable read performance, ~47% reduced read power, data retention of 20yrs (0.1 PPM), read disturb rate of <1 PPM for ~1M cycles with 500Oe field, 1M endurance cycles, and stand-by magnetic immunity (SMI) of ~1400Oe at 25°C and ~500Oe at 150°C (0.1 PPM). With magnetic shield-in package solution, we demonstrate ~4kOe SMI at 25°C for 48hrs of field exposure.

17 citations


Cited by
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Journal ArticleDOI
TL;DR: This Review surveys the four physical mechanisms that lead to resistive switching materials enable novel, in-memory information processing, which may resolve the von Neumann bottleneck and examines the device requirements for systems based on RSMs.
Abstract: The rapid increase in information in the big-data era calls for changes to information-processing paradigms, which, in turn, demand new circuit-building blocks to overcome the decreasing cost-effectiveness of transistor scaling and the intrinsic inefficiency of using transistors in non-von Neumann computing architectures. Accordingly, resistive switching materials (RSMs) based on different physical principles have emerged for memories that could enable energy-efficient and area-efficient in-memory computing. In this Review, we survey the four physical mechanisms that lead to such resistive switching: redox reactions, phase transitions, spin-polarized tunnelling and ferroelectric polarization. We discuss how these mechanisms equip RSMs with desirable properties for representation capability, switching speed and energy, reliability and device density. These properties are the key enablers of processing-in-memory platforms, with applications ranging from neuromorphic computing and general-purpose memcomputing to cybersecurity. Finally, we examine the device requirements for such systems based on RSMs and provide suggestions to address challenges in materials engineering, device optimization, system integration and algorithm design. Resistive switching materials enable novel, in-memory information processing, which may resolve the von Neumann bottleneck. This Review focuses on how the switching mechanisms and the resultant electrical properties lead to various computing applications.

564 citations

Journal ArticleDOI
18 Aug 2020
TL;DR: In this article, the potential of spintronics in four key areas of application (memory, sensors, microwave devices, and logic devices) is examined and the challenges that need to be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms.
Abstract: Spintronic devices exploit the spin, as well as the charge, of electrons and could bring new capabilities to the microelectronics industry However, in order for spintronic devices to meet the ever-increasing demands of the industry, innovation in terms of materials, processes and circuits are required Here, we review recent developments in spintronics that could soon have an impact on the microelectronics and information technology industry We highlight and explore four key areas: magnetic memories, magnetic sensors, radio-frequency and microwave devices, and logic and non-Boolean devices We also discuss the challenges—at both the device and the system level—that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms This Review Article examines the potential of spintronics in four key areas of application —memories, sensors, microwave devices, and logic devices — and discusses the challenges that need be addressed in order to integrate spintronic materials and functionalities into mainstream microelectronic platforms

417 citations

Journal ArticleDOI
TL;DR: The suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.
Abstract: In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I-V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.

145 citations

Journal ArticleDOI
TL;DR: In this paper, the authors survey the recent progresses in SRAM and RRAM-based CIM macros that have been demonstrated in silicon and discuss general design challenges of the CIM chips including analog-to-digital conversion bottleneck, variations in analog compute, and device non-idealities.
Abstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in hardware accelerator design for deep learning. The input vector and weight matrix multiplication, i.e., the multiply-and-accumulate (MAC) operation, could be performed in the analog domain within memory sub-array, leading to significant improvements in throughput and energy efficiency. Static random access memory (SRAM) and emerging non-volatile memories such as resistive random access memory (RRAM) are promising candidates to store the weights of deep neural network (DNN) models. In this review, firstly we survey the recent progresses in SRAM and RRAM based CIM macros that have been demonstrated in silicon. Then we discuss general design challenges of the CIM chips including analog-to-digital conversion (ADC) bottleneck, variations in analog compute, and device non-idealities. Next we introduce the DNN+NeuroSim benchmark framework that is capable of evaluating versatile device technologies for CIM inference and training performance from software/hardware co-design's perspective.

94 citations

Journal ArticleDOI
TL;DR: The technology that enabled present toggle and STT-MRAM products, future STT, and new MRAM technologies beyond STT are reviewed.
Abstract: Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

92 citations