J. Wong

Bio: J. Wong is an academic researcher from GlobalFoundries. The author has contributed to research in topics: Computer science. The author has an hindex of 1, co-authored 1 publications receiving 41 citations.

CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications

Abstract: Perpendicular Spin-Transfer Torque (STT) MRAM is a promising technology in terms of read/write speed, low power consumption and non-volatility, but there has not been a demonstration of high density manufacturability at small geometries. In this paper we present an unprecedented demonstration of a robust STT-MRAM technology designed in a 2x nm CMOS-embedded 40 Mb array. Key features are full array functionality with low BER (bit error rate), process uniformity and reliability, 10 years data retention at 125C with extended endurance to ∼ 107 cycles. All achieved with standard BEOL process temperatures. Data retention post 260°C solder reflow temperature cycle is demonstrated.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities

Abstract: We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet >1M cycles with solder reflows and path towards achieving >E12 cycles for cache applications.

STT-MRAM Product Reliability and Cross-Talk

Abstract: STT-MRAM has been showcased to be a viable solution to replace eFlash and SRAM technologies. With the increasing demand for connected edge computing and internet of things, the usage of STT-MRAM in MCU and MPU products has become the reality. The product reliability of industrial-grade (-40~125°C) 40Mb 22FDX® embedded-MRAM technology having 5x-solder reflows compatibility stack is presented. The stand-by magnetic immunity and cross-talk between MRAM and RF are also discussed.

Nanoscale resistive switching memory devices: a review.

Abstract: In this review the different concepts of nanoscale resistive switching memory devices are described and classified according to their I-V behaviour and the underlying physical switching mechanisms. By means of the most important representative devices, the current state of electrical performance characteristics is illuminated in-depth. Moreover, the ability of resistive switching devices to be integrated into state-of-the-art CMOS circuits under the additional consideration with a suitable selector device for memory array operation is assessed. From this analysis, and by factoring in the maturity of the different concepts, a ranking methodology for application of the nanoscale resistive switching memory devices in the memory landscape is derived. Finally, the suitability of the different device concepts for beyond pure memory applications, such as brain inspired and neuromorphic computational or logic in memory applications that strive to overcome the vanNeumann bottleneck, is discussed.

Magnetoresistive Random Access Memory: Present and Future

Abstract: Magnetoresistive random access memory (MRAM) is regarded as a reliable persistent memory technology because of its long data retention and robust endurance. Initial MRAM products utilized toggle mode writing of a balanced synthetic antiferromagnet (SAF) free layer to overcome problems with half-selected bits that challenged traditional Stoner–Wohlfarth switching. With the development of spin transfer torque (STT) switching in perpendicular magnetic tunnel junctions, the capability for scaling MRAM products increased markedly, enabling a 1-Gb device in 2019. Ongoing research will allow scaling to even higher capacities. Compared to traditional memories, STT-MRAM can save power, improve performance, and enhance system data integrity, which supports the growing computing demands for everything from data centers to Internet of Things (IoT) devices. This article provides a review of the technology that enabled present toggle and STT-MRAM products, future STT-MRAM products, and new MRAM technologies beyond STT.

Carbon nanomaterials for non-volatile memories

Abstract: Carbon nanomaterials have greatly advanced non-volatile memory technology. In this Review, applications of various carbon nanomaterials as memory electrodes, interfacial engineering layers, memory selectors and resistive-switching media are discussed in the context of emerging non-volatile memory devices.

The N3XT Approach to Energy-Efficient Abundant-Data Computing

Abstract: The world’s appetite for analyzing massive amounts of structured and unstructured data has grown dramatically. The computational demands of these abundant-data applications, such as deep learning, far exceed the capabilities of today’s computing systems and are unlikely to be met with isolated improvements in transistor or memory technologies, or integrated circuit architectures alone. To achieve unprecedented functionality, speed, and energy efficiency, one must create transformative nanosystems whose architectures are based on the salient properties of the underlying nanotechnologies. Our Nano-Engineered Computing Systems Technology (N3XT) approach makes such nanosystems possible through new computing system architectures leveraging emerging device (logic and memory) nanotechnologies and their dense 3-D integration with fine-grained connectivity to immerse computing in memory and new logic devices (such as carbon nanotube field-effect transistors for implementing high-speed and low-energy logic circuits) as well as high-density nonvolatile memory (such as resistive memory), and amenable to ultradense (monolithic) 3-D integration of thin layers of logic and memory devices that are fabricated at low temperature. In addition, we explore the use of several device and integration technologies in the N3XT beyond the specific ones mentioned earlier that are also used in our main nanosystem prototypes. We also present an efficient resiliency technique to overcome endurance challenges in certain resistive memory technologies. N3XT hardware prototypes demonstrate the practicality of our architectures. We evaluate the benefits of the N3XT using a simulation framework calibrated using experimental measurements. System-level energy-delay product of common implementations of abundant-data workloads improves by three orders of magnitude in the N3XT compared with conventional architectures. These improvements impact a broad range of application workloads and architecture configurations, from embedded systems to the cloud.

Memory technology-a primer for material scientists.

Abstract: From our own experience, we know that there is a gap to bridge between the scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. An understanding of the big picture is vital, so we first provide an overview of the development and architecture of memories as part of a computer and call attention to some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained, and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.