J
J.-Y. Yeh
Researcher at Intel
Publications - Â 8
Citations - Â 648
J.-Y. Yeh is an academic researcher from Intel. The author has contributed to research in topics: Transistor & Logic gate. The author has an hindex of 8, co-authored 8 publications receiving 611 citations.
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Proceedings ArticleDOI
A 22nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra low power, high performance and high density SoC applications
Chia-Hong Jan,Uddalak Bhattacharya,Ruth A. Brain,S.-J. Choi,G. Curello,G. Gupta,Hafez Walid M,M. Jang,M. Kang,K. Komeyli,T. Leo,Nidhi Nidhi,L. Pan,Joodong Park,Kinyip Phoa,Abdur Rahman,C. Staus,H. Tashiro,Curtis Tsai,P. Vandervoorn,L. Yang,J.-Y. Yeh,P. Bai +22 more
TL;DR: In this paper, a leading edge 22nm 3-D tri-gate transistor technology has been optimized for low power SoC products for the first time, and a low standby power 380Mb SRAM capable of operating at 2.6GHz with 10pA/cell standby leakages.
Proceedings ArticleDOI
A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications
C.-H. Jan,M. Agostinelli,M. Buehler,Zhanping Chen,S.-J. Choi,G. Curello,H. Deshpande,S. Gannavaram,Hafez Walid M,U. Jalan,M. Kang,Pramod Kolar,K. Komeyli,B. Landau,A. Lake,N. Lazo,Seung Hwan Lee,T. Leo,J. Lin,Nick Lindert,S. Ma,L. McGill,C. Meining,A. Paliwal,Joodong Park,K. Phoa,Ian R. Post,N. Pradhan,M. Prince,Abdur Rahman,J. Rizk,L. Rockford,G. Sacks,A. Schmitz,H. Tashiro,Curtis Tsai,P. Vandervoorn,J. Xu,L. Yang,J.-Y. Yeh,J. Yip,Kevin Zhang,Yuegang Zhang,P. Bai +43 more
TL;DR: The low gate leakage of the high-k gate dielectric enables the triple transistor architecture to support ultra low power, high performance, and high voltage tolerant I/O devices concurrently.
Proceedings ArticleDOI
RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications
Chia-Hong Jan,M. Agostinelli,H. Deshpande,Mohammed A El-Tanani,Hafez Walid M,U. Jalan,L. Janbay,M. Kang,Hasnain Lakdawala,J. Lin,Y-L Lu,S. Mudanai,Joodong Park,Abdur Rahman,Jad B. Rizk,W.-K. Shin,Krishnamurthy Soumyanath,H. Tashiro,Curtis Tsai,P. Vandervoorn,J.-Y. Yeh,P. Bai +21 more
TL;DR: In this article, the authors examined the impact of silicon technology scaling trends and associated technological innovations on RF CMOS device characteristics, and the application of novel strained silicon and high-k/metal gate technologies not only benefits digital systems, but significantly improves RF performance.
Proceedings ArticleDOI
A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors
C.-H. Jan,P. Bai,S. Biswas,M. Buehler,Zhanping Chen,G. Curello,S. Gannavaram,Hafez Walid M,Jun He,J. Hicks,U. Jalan,N. Lazo,J. Lin,Nick Lindert,C. Litteken,M. Jones,M. Kang,K. Komeyli,A. Mezhiba,S. Naskar,S. Olson,Joodong Park,Rachael J. Parker,L. Pei,Ian R. Post,N. Pradhan,Chetan Prasad,M. Prince,J. Rizk,G. Sacks,H. Tashiro,D. Towner,C. Tsai,Yih Wang,L. Yang,J.-Y. Yeh,J. Yip,Kaizad Mistry +37 more
TL;DR: A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products.
Proceedings ArticleDOI
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate
P. Vandervoorn,M. Agostinelli,S.-J. Choi,G. Curello,H. Deshpande,Mohammed A El-Tanani,Hafez Walid M,U. Jalan,L. Janbay,M. Kang,Kwang-Jin Koh,K. Komeyli,Hasnain Lakdawala,J. Lin,Nick Lindert,S. Mudanai,Joodong Park,K. Phoa,Abdur Rahman,Jad B. Rizk,L. Rockford,G. Sacks,Krishnamurthy Soumyanath,H. Tashiro,Stewart S. Taylor,Curtis Tsai,Hongtao Xu,J. Xu,L. Yang,Ian A. Young,J.-Y. Yeh,J. Yip,P. Bai,C.-H. Jan +33 more
TL;DR: A 32nm RF SOC technology is developed with high-k/metal-gate triple-transistor architecture simultaneously offering devices with high performance and very low leakage to address advanced RF/mobile communications markets.