Jaafar Chbili

Bio: Jaafar Chbili is an academic researcher from National Institute of Standards and Technology. The author has contributed to research in topics: Time-dependent gate oxide breakdown & Population. The author has an hindex of 4, co-authored 5 publications receiving 62 citations. Previous affiliations of Jaafar Chbili include SIDI.

Modeling Early Breakdown Failures of Gate Oxide in SiC Power MOSFETs

Abstract: One of the most serious technology roadblocks for SiC DMOSFETs is the significant occurrence of early failures in time-dependent-dielectric-breakdown testing. Conventional screening methods have proved ineffective, because the remaining population is still plagued with poor reliability. The traditional local thinning model for extrinsic (early) failures, which guides the screening through burn-in measures, simply does not work. The fact that improved cleanliness control in the fabrication process does little to reduce early failures also suggests that local thinning due to contamination is not the root cause. In this paper, we propose a new lucky defect model where bulk defects in the gate oxide, introduced during growth, are responsible for the early failures. We argue that a local increase in leakage current via trap-assisted tunneling leads to early oxide breakdown. This argument is supported with oxide breakdown observations in SiC/SiO2 DMOSFETs, as well as simulations that examine various defect distributions and their impact on the resultant early failure distributions.

Time Dependent Dielectric Breakdown in High Quality SiC MOS Capacitors

Abstract: In this paper we report TDDB results on SiO2/SiC MOS capacitors fabricated in a matured production environment. A key feature is the absence of early failure out of over 600 capacitors tested. The observed field accelerations and activation energies are higher than what is reported on SiO2/Si of similar oxide thickness. The great improvement in oxide reliability and the deviation from typical SiO2/SiC observations are explained by the quality of the oxide in this study.

Cloud Security Automation Framework

Abstract: Cloud services have gained tremendous attentionas a utility paradigm and have been deployed extensively across awide range of fields. However, Cloud security is not catching upto the fast adoption of its services and remains one of the biggestchallenges for Cloud Service Providers (CSPs) and Cloud ServiceConsumers (CSCs) from the industry, government, andacademia. These institutions are increasingly faced with threatssuch as DoS/DDoS attacks, ransomware attacks, and databreaches that are affecting the confidentiality, integrity, andavailability of the cloud system resources. In the current cloudsystems, security requires manual translation of securityrequirements into controls. Such an approach can be for themost part labor intensive, tedious, and error-prone leading toinevitable misconfigurations rendering the system-at-handvulnerable to misuse, either malicious or unintentional.Therefore, it is of utmost importance to automate theconfiguration of the cloud systems per the client’s securityrequirements steering clear from the caveats of the manualapproach. Furthermore, cloud systems need to be continuouslymonitored for any misconfigurations. This paper presents amethodology allowing for cloud security automation anddemonstrates how a cloud environment can be automaticallyconfigured to implement a set of NIST SP 800-53 securitycontrols. In addition, this paper shows how the implementationof these controls in the cloud systems can be continuouslymonitored and validated.

Massively parallel TDDB testing: SiC power devices

Abstract: This paper presents a novel experimental setup to perform wafer level TDDB testing. The massively parallel reliability system is capable of testing a total of 3000 probes simultaneously. The system can perform tests at temperatures up to 400 °C for high temperature applications (SiC). We also present TDDB results of SiO2 on SiC showing higher TDDB lifetime and field acceleration compared to SiO2 on Si.

Influence of lucky defect distributions on early TDDB failures in SiC power MOSFETs

Abstract: In this work, we explore the effect of different defect profiles on the occurrence of early time-dependent-dielectric-breakdown (TDDB) to forecast the defect profile present in commercial grade SiC/SiO 2 DMOSFETs. Early failure simulations are performed using the recently developed “lucky defect” model. The model shows that the bulk defects in the gate oxide are the likely culprit for early TDDB failures through an increase in tunneling current via trap-assisted-tunneling (TAT). We show that an exponential distribution of “lucky defects” in the oxide bulk affects the failure distribution in a similar fashion to what we observe experimentally. We also identify the implications of under-sampling the population in these extrinsically dominated failure distributions. Armed with these tools, we show that, the speculated carbon rich transition layer at or near the interface is not likely present in the measured DMOSFETs.

Performance and Reliability Review of 650 V and 900 V Silicon and SiC Devices: MOSFETs, Cascode JFETs and IGBTs

Abstract: The future of power conversion at low-to-medium voltages (around 650 V) poses a very interesting debate. At low voltages (below 100 V), the silicon (Si) MOSFET reigns supreme and at the higher end of the automotive medium-voltage application spectrum (approximately 1 kV and above) the SiC power MOSFET looks set to topple the dominance of the Si insulated-gate bipolar transistor (IGBT). At very high voltages (4.5 kV, 6.5 kV and above) used for grid applications, the press-pack thyristor remains undisputed for current source converters and the press-pack IGBTs for voltage source converters. However, around 650 V, there does not seem to be a clear choice with all the major device manufacturers releasing different technology variants ranging from SiC Trench MOSFETs, SiC Planar MOSFETs, cascode-driven WBG FETs, silicon NPT and Field-stop IGBTs, silicon super-junction MOSFETs, standard silicon MOSFETs, and enhancement mode GaN high electron mobility transistors (HEMTs). Each technology comes with its unique selling point with gallium nitride (GaN) being well known for ultrahigh speed and compact integration, SiC is well known for high temperature, electro-thermal ruggedness, and fast switching while silicon remains clearly dominant in cost and proven reliability. This article comparatively assesses the performance of some of these technologies, investigates their body diodes, discusses device reliability, and avalanche ruggedness.

Review and analysis of SiC MOSFETs’ ruggedness and reliability

Abstract: SiC MOSFETs (silicon carbide metal-oxide semiconductor field-effect transistors) are replacing Si insulated gate bipolar transistors in many power conversion applications due to their superior performance. However, ruggedness and reliability of SiC MOSFETs are still big concern for their widespread applications in the market, especially in safety-critical applications. The objective of this study is to provide a comprehensive picture on the ruggedness and reliability of commercial SiC MOSFETs, discover their failure or degradation mechanism, and propose some possible mitigation methods through both literature survey and in-depth analysis. The ruggedness of SiC MOSFETs discussed here includes short-circuit (SC) ruggedness, avalanche ruggedness, and their failure mechanism. The reliability issues include gate oxide reliability, degradation under high-temperature bias stress, repetitive SC stress, avalanche stress, power cycling stress, body diode's surge current stress, and their degradation mechanism. Furthermore, this study discusses methods and solutions to improve their ruggedness and reliability.

A Novel Non-Intrusive Technique for BTI Characterization in SiC mosfet s

Abstract: Threshold voltage ( V TH) shift due to bias temperature instability (BTI) is a well-known problem in SiC mosfet s that occurs due to oxide traps in the SiC/SiO2 gate interface. The reduced band offsets and increased interface/fixed oxide traps in SiC mosfet s makes this a more critical problem compared to silicon. Before qualification, power devices are subjected to gate bias stress tests after which V TH shift is monitored. However, some recovery occurs between the end of the stress and V TH characterization, thereby potentially underestimating the extent of the problem. In applications where the SiC mosfet module is turned off with a negative bias at high temperature, if the V TH shift is severe enough, there may be electrothermal failure due to current crowding since parallel devices lose synchronization during turn- on . In this paper, a novel method that uses the forward voltage of the body diode during reverse conduction of a small sensing current is introduced as a technique for monitoring V TH shift and recovery due to BTI. This non-invasive method exploits the increased body effect that is peculiar to SiC mosfet s due to the higher body diode forward voltage. With the proposed method, it is possible to non-invasively assess V TH shift dynamically during BTI characterization tests.