Jacques-Olivier Klein

Bio: Jacques-Olivier Klein is an academic researcher from Université Paris-Saclay. The author has contributed to research in topics: CMOS & Artificial neural network. The author has an hindex of 36, co-authored 196 publications receiving 4750 citations. Previous affiliations of Jacques-Olivier Klein include University of Paris-Sud & University of Paris.

Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions

Abstract: Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems

Abstract: Spin-transfer torque magnetic memory (STT-MRAM) is currently under intense academic and industrial development, since it features non-volatility, high write and read speed and high endurance. In this work, we show that when used in a non-conventional regime, it can additionally act as a stochastic memristive device, appropriate to implement a “synaptic” function. We introduce basic concepts relating to spin-transfer torque magnetic tunnel junction (STT-MTJ, the STT-MRAM cell) behavior and its possible use to implement learning-capable synapses. Three programming regimes (low, intermediate and high current) are identified and compared. System-level simulations on a task of vehicle counting highlight the potential of the technology for learning systems. Monte Carlo simulations show its robustness to device variations. The simulations also allow comparing system operation when the different programming regimes of STT-MTJs are used. In comparison to the high and low current regimes, the intermediate current regime allows minimization of energy consumption, while retaining a high robustness to device variations. These results open the way for unexplored applications of STT-MTJs in robust, low power, cognitive-type systems.

Perpendicular-anisotropy magnetic tunnel junction switched by spin-Hall-assisted spin-transfer torque

Abstract: We investigate the magnetization switching induced by spin-Hall-assisted spin-transfer torque (STT) in a three-terminal device consisting of a perpendicular-anisotropy magnetic tunnel junction (MTJ) and an β-W strip. Magnetization dynamics in free layer of MTJ is simulated by solving numerically a modified Landau–Lifshitz–Gilbert equation. The influences of spin-Hall write current (density, duration and direction) on the STT switching are evaluated. We find that the switching speed of a STT-MTJ can be significantly improved (reduced to <1 ns) by using a sufficiently large spin-Hall write current density (~25 MA cm−2) with an appropriate duration (~0.5 ns). Finally we develop an electrical model of three-terminal MTJ/β-W device with Verilog-A language and perform transient simulation of switching a 4 T/1MTJ/1β-W memory cell with Spectre simulator. Simulation results demonstrate that spin-Hall-assisted STT-MTJ has advantages over conventional STT-MTJ in write speed and energy.

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology

Abstract: Conventional MOS integrated circuits and systems suffer serve power and scalability challenges as technology nodes scale into ultra-deep-micron technology nodes (e.g., below 40nm). Both static and dynamic power dissipations are increasing, caused mainly by the intrinsic leakage currents and large data traffic. Alternative approaches beyond charge-only-based electronics, and in particular, spin-based devices, show promising potential to overcome these issues by adding the spin freedom of electrons to electronic circuits. Spintronics provides data non-volatility, fast data access, and low-power operation, and has now become a hot topic in both academia and industry for achieving ultra-low-power circuits and systems. The ITRS report on emerging research devices identified the magnetic tunnel junction (MTJ) nanopillar (one of the Spintronics nanodevices) as one of the most promising technologies to be part of future micro-electronic circuits. In this review we will give an overview of the status and prospects of spin-based devices and circuits that are currently under intense investigation and development across the world, and address particularly their merits and challenges for practical applications. We will also show that, with a rapid development of Spintronics, some novel computing architectures and paradigms beyond classic Von-Neumann architecture have recently been emerging for next-generation ultra-low-power circuits and systems.

PRIME: a novel processing-in-memory architecture for neural network computation in ReRAM-based main memory

Abstract: Processing-in-memory (PIM) is a promising solution to address the "memory wall" challenges for future computer systems. Prior proposed PIM architectures put additional computation logic in or near memory. The emerging metal-oxide resistive random access memory (ReRAM) has showed its potential to be used for main memory. Moreover, with its crossbar array structure, ReRAM can perform matrix-vector multiplication efficiently, and has been widely studied to accelerate neural network (NN) applications. In this work, we propose a novel PIM architecture, called PRIME, to accelerate NN applications in ReRAM based main memory. In PRIME, a portion of ReRAM crossbar arrays can be configured as accelerators for NN applications or as normal memory for a larger memory space. We provide microarchitecture and circuit designs to enable the morphable functions with an insignificant area overhead. We also design a software/hardware interface for software developers to implement various NNs on PRIME. Benefiting from both the PIM architecture and the efficiency of using ReRAM for NN computation, PRIME distinguishes itself from prior work on NN acceleration, with significant performance improvement and energy saving. Our experimental results show that, compared with a state-of-the-art neural processing unit design, PRIME improves the performance by ~2360× and the energy consumption by ~895×, across the evaluated machine learning benchmarks.

Synaptic electronics: materials, devices and applications

Abstract: In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

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