Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a selected cyclic redundancy check generator polynomial, at least one cyclic redundancy check is calculated based upon a first subset of the plurality of bits with a certain bit ordering, and at least another cyclic redundancy check is calculated based upon a second subset of the plurality of bits with a different bit ordering. The second subset of bits may overlap with the first subset of bits. In another aspect, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a plurality of different cyclic redundancy check generator polynomials. A first cyclic redundancy check generator polynomial is used for calculating a first cyclic redundancy check based upon a first plurality of bits, and a second cyclic redundancy check generator polynomial is used for calculating a second cyclic redundancy check based upon a second plurality of bits.

Methods and apparatus to generate multiple CRCs

A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

Transmission apparatus and method, reception apparatus and method, and program

An adjustable filter is responsive to a control signal to change a frequency response of the adjustable filter based on frequency spectrum information. The control signal may shift a center of the pass band from a first center frequency to a second center frequency and/or change a pass band bandwidth from a first bandwidth to a second bandwidth. In one example, the frequency spectrum information includes a status of an internal secondary radio. The frequency spectrum information may also indicate a region of operation where the frequency response is selected in accordance with the region.

Adjustable receive filter responsive to frequency spectrum information

This papers proposes to compress state metrics in turbo decoder architectures to reduce the decoder area. Two techniques are proposed: the first is based on non-uniform quantization and the second on the Walsh-Hadamard transform followed by non-uniform quantization. The non-uniform quantization technique reduces state metric memory area of about 50% compared with architectures where state metric compression is not performed, at the expense of slightly increasing the error correcting performance floor. On the other hand, the Walsh-Hadamard transform based solution offers a good tradeoff between performance loss and memory complexity reduction, which reaches in the best case 20% of gain with respect to other approaches. Both solutions show lower power consumption than architectures previously proposed to compress state metrics.

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State Metric Compression Techniques for Turbo Decoder Architectures

Low-power transmitter and/or receiver devices are provided by sacrificing time and/or frequency diversity in exchange for lower power consumption. When channel conditions indicate that time and/or frequency spreading are unnecessary for transmissions, a transmitter may enter into a power-conservation mode in which transmissions are performed using a time gating scheme or a time repetition scheme. In the time gating scheme, symbols are transmitting just once, rather than a plurality of times, but with increased transmission power. In the time repetition scheme, copies of the same symbol are transmitted a plurality of times on the same frequency on different symbol transmission periods, instead of being retransmitted on different frequencies on different symbol transmission periods. Consequently, the symbol can be generated once and stored for subsequent retransmission, thereby allowing some of the transmitter/receiver chain components can be operated at a lower duty cycle or processing speed to conserve power.

Low power ultra wideband transceivers

A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, creating a generation expression with respect to points in time that are sequentially delayed as much as the number of multi-channels from the first point in time by applying each point in time to the generation expression, and embodying a circuit corresponding to the generation expression with respect to the most delayed point in time among the created generation expressions. The CRC circuit corresponding to the generation expression will have more modulo-2 adders (e.g., XOR gates) than the number of non-zero coefficients in the selected CRC polynomial.

Cyclic redundancy check circuit and communication system having the same for multi-channel communication

Two methods are presented that can substantially reduce the memory requirements of non-binary turbo decoders by efficient representation of the extrinsic information. In the case of the duo-binary turbo decoder employed by the IEEE 802.16e standard, the extrinsic information can be reduced by about 43%, which decreases the total decoder complexity by 18%. We also show that the proposed algorithm can be implemented by simple hardware architecture.

Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation

A method for demodulating an ultra-wide band (UWB) signal includes detecting a detecting a data rate of the UWB signal, selecting one from plurality of clock signals in response to the detected data rate, decoding the UWB signal in accordance with the selected clock signal, and outputting transmission data determined by a fast clock. The plurality of clock signals includes at least one frequency different from other frequencies. A receiver for an UWB signal includes an OFDM demodulating unit demodulating the UWB signal into an OFDM symbol, and a bit-level processing unit demodulating the OFDM symbol into bit-level data. The bit-level processing unit receives a scaled clock signal having a frequency corresponding to one of a plurality of data rates of the UWB signal. The method and apparatus may reduce static power consumption and improve performance of the receiver.

UWB receiver scaling clock frequency by data rate and data reception method thereof

Encoding inputs corresponding to a set of powers of state matrix is added. Powers of state matrix have period T. The set of the powers of the state matrix has an identical state matrix value. One of the powers of the state matrix is multiplied by input matrix and the added encoding inputs. Multiplied results are added so as to find last state of the turbo encoder. The last state corresponds to encoding state of the turbo encoder when the turbo encoding is started at zero state. Final state of the turbo encoder is found using the last state. The final state is identical to initial state of the turbo encoder, and corresponds to encoding state of the turbo encoder when turbo encoding is started with the initial state. Encoding inputs are encoded using the final state.

Method of finding a last state in tail-biting for turbo encoder and apparatus using the same

An interface through which a decoder chip, which pre-processes an image, transmits on screen display (OSD) data to a display chip, which post-processes the image, in a digital broadcast receiving device. The decoder chip generates and transmits an interrupt to the display chip which operates as a host, and when a read command is received from the display chip, the decoder chip reads OSD data from an external memory so as to transmit the OSD data to the display chip. Accordingly, OSD data can be transmitted to the display chip operating as a host using a path different from the image data path.

Jae-Young Kwak

Papers

Cyclic redundancy check circuit and communication system having the same for multi-channel communication

Extrinsic Information Memory Reduced Architecture for Non-Binary Turbo Decoder Implementation

UWB receiver scaling clock frequency by data rate and data reception method thereof

Method of finding a last state in tail-biting for turbo encoder and apparatus using the same

On screen display interface for digital broadcast receiving device