Jafar Savoj

Bio: Jafar Savoj is an academic researcher from Rambus. The author has contributed to research in topics: Digital-to-analog converter & Wideband. The author has an hindex of 6, co-authored 10 publications receiving 144 citations. Previous affiliations of Jafar Savoj include Apple Inc..

Receiver with enhanced clock and data recovery

Abstract: A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler.

A 24 Gb/s Software Programmable Analog Multi-Tone Transmitter

Abstract: A 24 Gb/s transmitter employs a digital linear equalizer and a 12 GS/s 8-bit digital-to-analog converter (DAC). Implemented in a 90 nm CMOS technology, the transmitter can be programmed to support a variety of communication modes including 4-channel and 2-channel analog multi-tone (AMT), as well as various baseband (BB) modes ranging from 2 to 256 PAM. Selection of the transmission mode is enabled through software programming of the appropriate tap coefficients into the equalizer. The transmitter dissipates 510 mW of power and is fabricated over an area of 0.8 mm. Experimental results confirm clear eye diagrams at 28 Gb/s.

A 24Gb/s Software Programmable Multi-Channel Transmitter

Abstract: A 24Gb/s transmitter with a digital linear equalizer is implemented in 90 nm CMOS technology. It supports 4-channel Analog Multi-Tone (AMT) transmission, where each channel supports 3 GSym/Sec 4 PAM data, as well as a variety of baseband (BB) modes ranging from 2 PAM to 256 PAM. The transmitter operates at maximum rate of 24 Gb/s, dissipating 51 OmW of power in 0.8 mm2

A new technique for characterization of digital-to-analog converters in high-speed systems

Abstract: In this paper, a new technique for characterization of digital-to-analog converters (DAC) used in wideband applications is described. Unlike the standard narrowband approach, this technique employs Least Square Estimation to characterize the DAC from dc to any target frequency. Characterization is performed using a random sequence with certain temporal and probabilistic characteristics suitable for intended operating conditions. The technique provides a linear estimation of the system and decomposes nonlinearity into higher-order harmonics and deterministic periodic noise. The technique can also be used to derive the impulse response of the converter, predict its operating bandwidth, and provide far more insight into its sources of distortion.

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter

Abstract: A 12-GS/s 8-bit Digital-to-Analog Converter (DAC) enables 24 Gb/s signaling over conventional backplane channels. Designed in a 90-nm CMOS process, the circuit occupies an area of 670 mum times 350mum and achieves INL and DNL of 0.31 and 0.28 LSB. Measured SNDR and SFDR are 41 dB and 51 dB at 750 MHz and 32.5 dB and 35 dB at 1.5 GHz. The power dissipation is 190 mW from 1-V and 1.8-V power supplies.

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

Abstract: This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

General Analysis on the Impact of Phase-Skew in Time-Interleaved ADCs

Abstract: Time-interleaved analog-to-digital converters (TIADCs) are sensitive to various mismatches that distort the sampled signal. Standard TIADC analysis assumes a narrowband sinusoidal input, which may result in pessimistic matching constraints for system-specific ADCs used with wideband input signals. Closed-form expressions bounding the acceptable phase-skew for wideband systems are derived and are validated through simulations. In one of the examples presented, it is shown that standard analysis can overconstrain the bound on acceptable phase-skew variance by a factor of three.

Modeling and Analysis of High-Speed I/O Links

Abstract: Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory

Abstract: Modern optical systems increasingly rely on DSP techniques for data transmission at 40Gbs and recently at 100Gbs and above. A significant challenge towards CMOS TX DSP SoC integration is due to requirements for four 6b DACs (Fig. 10.8.1) to operate at 56Gs/s with low power and small footprint. To date, the highest sampling rate of 43Gs/s 6b DAC is reported in SiGe BiCMOS process [1]. CMOS DAC implementations are constraint to 12Gs/s with the output signal frequency limited to 1.5GHz [2–4]. This paper demonstrates more than one order of magnitude improvement in 6b CMOS DAC design with a test circuit operating at 56Gs/s, achieving SFDR >30dBc and ENOB>4.3b up to the output frequency of 26.9GHz. Total power dissipation is less than 750mW and the core DAC die area is less than 0.6×0.4 mm2.

Distributed Waveform Generator: A New Circuit Technique for Ultra-Wideband Pulse Generation, Shaping and Modulation

Abstract: A new circuit technique, the distributed waveform generator (DWG), is proposed for low-power ultra-wideband pulse generation, shaping and modulation. It time-interleaves multiple impulse generators, and uses distributed circuit techniques to combine generated wideband impulses. Built-in pulse shaping can be realized by programming the delay and amplitude of each impulse similar to an FIR filter. Pulse modulation schemes such as on-off keying (OOK) and pulse position modulation (PPM) can be easily applied in this architecture. Two DWG circuit prototypes were implemented in a standard 0.18 mum digital CMOS technology to demonstrate its advantages. A 10-tap, 10 GSample/s, single-polarity DWG prototype achieves a pulse rate of 1 GHz while consuming 50 mW, and demonstrates OOK modulation using 16 Mb/s PRBS data. A 10-tap, 10 GSample/s, dual-polarity DWG prototype was developed to generate UWB pulses compliant with the transmit power emission mask. Based on the latter DWG design, a reconfigurable impulse radio UWB (IR-UWB) transmitter prototype was implemented. The transmitter's pulse rate can be varied from 16 MHz range up to 2.5 GHz. The bandwidth of generated UWB pulses is also variable, and was measured up to 6 GHz (- 10 dB bandwidth). Both OOK and PPM modulation schemes are successfully demonstrated using 32 Mb/s PRBS data. The IR-UWB transmitter achieves a measured energy efficiency of 45 pJ/pulse, independent of pulse rate.