Jahnavi Sharma

Bio: Jahnavi Sharma is an academic researcher from Intel. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 8, co-authored 16 publications receiving 231 citations. Previous affiliations of Jahnavi Sharma include Columbia University & IBM.

Calibration-Kit Design for Millimeter-Wave Silicon Integrated Circuits

Abstract: We study and present design guidelines for thru-reflect-line vector-network-analyzer calibration kits used for characterizing circuits and transistors fabricated on silicon integrated circuits at millimeter-wave frequencies. We compare contact-pad designs and develop fixed-fill contacts that achieve both repeatable and low contact-pad capacitances. We develop a fill-free and mesh-free transmission line structure for the calibration kit and compare it to similar transmission lines with meshed ground plane. We also develop a gold plating process that greatly improves contact repeatability, permitting the use of redundant multiline calibrations. This in turn simplifies the development of an error analysis. Finally, we apply the technique to state-of-the-art transistor characterization, and present measured results with uncertainties.

216- and 316-GHz 45-nm SOI CMOS Signal Sources Based on a Maximum-Gain Ring Oscillator Topology

Abstract: This paper introduces a maximum-gain ring oscillator (MGRO) topology that maximizes the power gain (PG) achieved by the active devices in a ring oscillator using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with expressions for the passive matching elements. In the absence of passive losses, the topology can oscillate at the fmax of the active devices. In the presence of passive loss, for the first time, the losses can be taken into account in a closed-form fashion to maximize device PG, and consequently, oscillation frequency. Based on this topology, two different oscillators operating at approximately 108 and 158 GHz are implemented using the 56-nm body-contacted devices (fmax ≈ 200 GHz) of IBM's 45-nm silicon-on-insulator CMOS technology. The fact that these two oscillators function well with marginal startup gains of 2.62 and 0.62 dB, respectively, demonstrates the robustness of the techniques described here. The second harmonic of the oscillation is extracted using a load-pull-optimized extraction network. This topology can be generalized for the extraction of any harmonic from MGROs with a different number of stages. The oscillators generate -14.4 dBm at 216.2 GHz and -21 dBm at 316.5 GHz while drawing 57.5 and 46.4 mW of dc power, respectively. This paper also describes the modeling of CMOS active and passive devices for high millimeter-wave and sub-millimeter-wave integrated-circuit design.

A 2.4-GHz Reference-Sampling Phase-Locked Loop That Simultaneously Achieves Low-Noise and Low-Spur Performance

Abstract: Dividerless synthesizers such as sub-sampling phase-locked loops (PLLs) and injection-locked clock multipliers have demonstrated some of the lowest jitters for a given power consumption (jitter-power ${\text {FoM}}_{j}$ metric). However, they contain a tradeoff between the spur and noise performance, where techniques incorporated for spur reduction adversely affect jitter or power performance. A new dividerless Type-I sampling PLL, called the reference sampling PLL (RS-PLL), which estimates the voltage-controlled oscillator (VCO) phase error by sampling the reference sine wave with a VCO square wave is demonstrated. A clock-and-isolation buffer which accelerates the VCO sine wave to a square wave sampling clock and simultaneously isolates the VCO tank from spur mechanisms in the sampler is included in place of a traditional reference buffer. By combining sampling clock buffer and VCO isolation functionalities into a single block, the RS-PLL eliminates the noise penalty of two separate buffers. The power penalty due to sampling at VCO frequency is restricted by limiting the activity of the switching circuits to the region around the reference zero crossing where the phase error information exists. The prototype RS-PLL implemented in 65-nm CMOS achieves a jitter-power ${\text {FoM}}_{j}$ of <−251 dB between 2.05 and 2.55 GHz with a reference spur of <−66 dBc at 50 MHz. In doing so, it improves upon the simultaneous noise and spur performance achieved by current state-of-the-art clock multipliers.

Silicon Optical Phased Array with Grating Lobe-Free Beam Formation Over 180 Degree Field of View

Abstract: Using index-mismatched waveguides, we demonstrate the first optical phased array with half-wavelength emitter pitch. We show operation without grating lobes over an entire 180° field of view and beam formation up to 60° off-axis.

Calibrations for Millimeter-Wave Silicon Transistor Characterization

Abstract: This paper compares on-wafer thru-reflect-line (TRL) and off-wafer short-open-load-thru (SOLT) and line-reflect-reflect-match (LRRM) vector-network-analyzer probe-tip calibrations for amplifier characterization and parasitic-extraction calibrations for transistor characterization on silicon integrated circuits at millimeter-wave frequencies We show that on-wafer calibrations generally outperform off-wafer and LRRM probe-tip calibrations at millimeter-wave frequencies However, certain parasitic-extraction algorithms designed specifically to remove contact pads, transmission-lines, and access vias correct for much of the error in off-wafer calibrations

IEEE Transactions on Microwave Theory and Techniques and Antennas and Propagation Announce a Joint Special Issue on Ultra-Wideband (UWB) Technology

Abstract: Before the emergence of ultra-wideband (UWB) radios, widely used wireless communications were based on sinusoidal carriers, and impulse technologies were employed only in specific applications (e.g. radar). In 2002, the Federal Communication Commission (FCC) allowed unlicensed operation between 3.1–10.6 GHz for UWB communication, using a wideband signal format with a low EIRP level (−41.3dBm/MHz). UWB communication systems then emerged as an alternative to narrowband systems and significant effort in this area has been invested at the regulatory, commercial, and research levels.

Long-Range LiDAR and Free-Space Data Communication With High-Performance Optical Phased Arrays

Abstract: We present high-performance integrated optical phased arrays along with first-of-their-kind light detection and ranging (LiDAR) and free-space data communication demonstrators. First, record-performance optical phased array components are shown with low-power phase shifters and high-directionality waveguide grating antennas. Then, one-dimensional (1-D) 512-element optical phased arrays are demonstrated with record low-power operation ( $ 1 mW total), large steering ranges, and high-speed two-dimensional (2-D) beam steering ( $ 30 $\mu$ s phase shifter time constant). Next, by utilizing optical phased arrays, we show coherent 2-D solid-state LiDAR on diffusive targets with simultaneous velocity extraction at a range of nearly 200 m. In addition, the first demonstration of 3-D coherent LiDAR with optical phased arrays is presented with raster-scanning arrays. Finally, lens-free chip-to-chip free-space optical communication links up to 50 m are shown, including a demonstration of a steerable transmitter to multiple optical phased array receivers at a 1 Gb/s data rate. This paper shows the most advanced silicon photonics solid-state beam steering to date with relevant demonstrators in practical applications.

SiGe HBT Technology: Future Trends and TCAD-Based Roadmap

Abstract: A technology roadmap for the electrical performance of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) is presented based on combining the results of various 1-D, 2-D, and 3-D technology computer-aided design (TCAD) simulation tools with geometry scalable compact modeling. The latter, including all known parasitic effects, enables the accurate determination of the figures of merit for both devices and selected benchmark circuits. The presented roadmap defines five major technology nodes with the maximum oscillation frequency of a typical high-frequency device structure as the main device design target under the constraints of various other parameters for generating the doping profiles and for defining the lateral scaling factors. An extensive and consistent set of technology and electrical parameters is provided along with the obtained scaling rules. The expected fabrication-related challenges and possible solutions for achieving the predicted performance are being discussed. It is hoped that the presented roadmap will be useful not only for foundries and equipment manufacturers but also for circuit and system designers enabling better predictions of the capability of SiGe–BiCMOS process technology for new millimeter-wave (mm-wave) and terahertz (THz) applications.

A 60 GHz CMOS Full-Duplex Transceiver and Link with Polarization-Based Antenna and RF Cancellation

Abstract: This paper presents a fully integrated 60 GHz direct-conversion transceiver in 45 nm SOI CMOS for same-channel full-duplex (FD) wireless communication. FD operation is enabled by a novel polarization-based wideband reconfigurable self-interference cancellation (SIC) technique in the antenna domain. The antenna cancellation can be reconfigured from the IC to combat the variable SI scattering from the environment during in-field operation. A second RF cancellation path with $ > 30\;\text{dB}$ gain control and $ > 360^{\circ}$ phase control from the transmitter (TX) output to the LNA output further suppresses the residual SI to achieve the high levels of required SIC. With antenna and RF cancellation together, a total SI suppression of $ > 70\;\text{dB}$ is achieved over a cancellation bandwidth of 1 GHz and can be maintained in the presence of nearby reflectors. In conjunction with digital SIC (DSIC) implemented in MATLAB, a FD link is demonstrated over 0.7 m with a signal-to-interference-noise-and-distortion ratio (SINDR) of 7.2 dB. To the best of our knowledge, this work achieves the highest integration level among FD transceivers irrespective of the operation frequency and demonstrates the first fully integrated mm-wave FD transceiver front-end and link.

High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation

Abstract: Series stacking of multiple devices is a promising technique that can help overcome some of the fundamental limitations of CMOS technology in order to improve the output power and efficiency of CMOS power amplifiers (PAs), particularly at millimeter-wave (mmWave) frequencies. This paper investigates the concept of device stacking in the context of the Class-E family of nonlinear switching PAs at mmWave frequencies. Fundamental limits on achievable performance of a stacked configuration are presented along with design guidelines for a practical implementation. In order to demonstrate the utility of stacking, three prototypes have been implemented: two fully integrated 45-GHz single-ended Class-E-like PAs with two- and four-stacked devices in IBM's 45-nm silicon-on-insulator (SOI) CMOS technology, and a 45-GHz differential Class-E-like PA with two devices stacked in IBM's 65-nm low-power CMOS process. Measurement results yield a peak power-added efficiency (PAE) of 34.6% for the two-stacked 45-nm SOI CMOS PA with a saturated output power of 17.6 dBm. The measurement results also indicate true Class-E-like switching PA behavior. A peak PAE of 19.4% is measured for the four-stacked PA with a saturated output power of 20.3 dBm. The two-stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOS mmWave PA including those that employ power combining. The 65-nm CMOS differential two-stacked PA exhibits a peak PAE of 28.3% with a saturated differential output power of 18.2 dBm, despite the poor ON-resistance of the 65-nm low-power nMOS devices. This paper also describes the modeling of active devices for mmWave CMOS PAs for good model-hardware correlation.