Showing papers by "Jai Narayan Tripathi published in 2017"
TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Abstract: An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented. Semianalytical expressions for jitter are derived based on separating the large signal response and the small signal noise response and subsequently combining the results. Proposed simplified relations enable the designers to estimate the PSIJ based on a single bit simulation. Proposed methods are validated on several examples of voltage-mode driver circuits, designed in different technologies and in the presence of different types of noise sources.
30 citations
01 May 2017
TL;DR: In this paper, an optimal decoupling network is designed by Simulated Annealing to reduce the power supply noise in power delivery networks, which reduces the cumulative impedance of power delivery network.
Abstract: An efficient methodology for minimizing core supply noise in Power Delivery Networks is presented. To reduce the power supply noise, an optimal decoupling network is designed by Simulated Annealing. The cumulative impedance of Power Delivery Network is reduced using lesser number of decoupling capacitors compared to placing decoupling capacitors intuitively. The supply noise is minimized according to the requirement of system specifications and the corresponding jitter reduction is reported.
19 citations
TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.
Abstract: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.
13 citations
TL;DR: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach and reports a significant speed-up reported compared with the simulations by a commercial simulator.
Abstract: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach. The methodology is described in detail through an example of a voltage-mode driver circuit. There is a significant speed-up reported compared with the simulations by a commercial simulator.
12 citations
01 Dec 2017
TL;DR: Harmonic distortion associated with a 12 V to 1.2 V open-loop buck converter (designed in the BCD 180 nm technology of STMicroelectronics) has been analyzed and the nonlinear behavior of a buck converter has been modeled using Volterra series for expected power supply ripples of 50 Hz.
Abstract: The presence of harmonic components in a power delivery network affects the performance of the high-speed systems. In this paper, harmonic distortion associated with a 12 V to 1.2 V open-loop buck converter (designed in the BCD 180 nm technology of STMicroelectronics) has been analyzed. The nonlinear behavior of a buck converter has been modeled using Volterra series for expected power supply ripples of 50 Hz. The analysis has been compared with simulation results and shows 5 %, 1 % and 7 % of mean relative error. The difference between the analytical and the simulation results for IP 2h and IP3 h are 2.7 dB and 3 dB, respectively.
5 citations
01 Dec 2017
TL;DR: The proposed semi-analytical method for jitter analysis is compared against the conventional simulations (commercial tools) in a 55nm technology of STMicroelectronics to find a reasonable matching.
Abstract: In this paper, a method is presented to estimate the effect of transmission media on power supply induced jitter for a voltage-mode driver circuit Transmission media is represented via its equivalent models of transmission lines while calculating the power supply induced jitter The proposed semi-analytical method for jitter analysis is compared against the conventional simulations (commercial tools) in a 55nm technology of STMicroelectronics A reasonable matching is reported
3 citations
01 Nov 2017
TL;DR: From the analysis, the results are 96 %, 97 % and 90 % matched with the simulation results when the amplitude of the input ripple varies from 0 V to 1.8 V.
Abstract: This paper presents design and harmonic distortion analysis using Volterra series for a 12 V to 1.2 V buck converter designed in the 180 nm BCD8 technology of STMicroelectronics. The series determines the closed-form equations for fundamental, second and third harmonics. From the analysis, the results are 96 %, 97 % and 90 % matched with the simulation results when the amplitude of the input ripple varies from 0 V to 1.8 V.
2 citations
01 Dec 2017
TL;DR: In this article, a nonlinear distortion analysis of power delivery network and the impact of nonlinear characteristics of DC-DC converter on the PDN output have been analyzed The harmonic components for an equivalent PDN model have been estimated using Volterra series for 50 Hz input ripples.
Abstract: In this paper, a nonlinear distortion analysis of power delivery network and the impact of nonlinear characteristics of DC-DC converter on the PDN output have been analyzed The harmonic components for an equivalent PDN model have been estimated using Volterra series for 50 Hz input ripples The mean relative error between analytical and simulated results for the fundamental (H 1 (jω 1 )), the second (H 2 (jω 1 , jω 2 )) and the third harmonic (H 2 (jω 1 , jω 2 , jω 3 )) responses are 3%, 1% and 7%, respectively For input intercept points (IIP 2 and IIP 3 ), the difference between analytical and simulation results are 05 dB and 28 dB, respectively